728981DBG Renesas

IDT728981 TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128 outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form FEATURES: a multiplexed 2.048 Mb/s stream. 128 x 128 channel non-blocking switch Serial Telecom Bus Compatible (ST-BUS ) FUNCTIONAL DESCRIPTION 4 RX inputs32 channels at 64 Kbit/s per serial line 4 TX output32 channels at 64 Kbit/s per serial line A functional block diagram of the IDT728981 device is shown below. The Three-state serial outputs serial streams operate continuously at 2.048 Mb/s and are arranged in 125s Microprocessor Interface (8-bit data bus) wide frames each containing 32, 8-bit channels. Four input (RX0-3) and four 5V Power Supply output (TX0-3) serial streams are provided in the IDT728981 device allowing Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin a complete 128 x 128 channel non-blocking switch matrix to be constructed. Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP) The serial interface (C4i) clock for the device is 4.096 MHz. Operating Temperature Range -40C to +85C The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 128-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, DESCRIPTION: F0i, the incoming serial data streams can be framed and sequentially ad- The IDT728981 is a ST-BUS compatible digital switch controlled by a dressed. microprocessor. The IDT728981 can handle as many as 128, 64 Kbit/s input and output channels. Those 128 channels are divided into 4 serial inputs and FUNCTIONAL BLOCK DIAGRAM ODE C4i F0i VCC GND Timing Unit Output MUX RX0 TX0 Transmit Receive RX1 TX1 Data Serial Data Serial Data Memory Streams Streams TX2 RX2 TX3 RX3 Connection Control Register Memory Microprocessor Interface 5703 drw01 DS CS A0/ R/W DTA D0/ A5 D7 JANUARY 2001 1 DSC-5703/1IDT728981 Time Slot Interchange Commercial Temperature Range Digital Switch 128 x 128 PIN CONFIGURATION INDEX INDEX RX3 7 39 TX3 RX3 1 33 TX3 (1) VCC 8 38 DNC (1) VCC DNC 2 32 (1) VCC 9 37 (1) DNC VCC 3 31 DNC (1) VCC 36 (1) 10 DNC VCC 4 DNC 30 VCC (1) (1) 11 35 DNC VCC 5 29 DNC VCC 6 28 GND VCC 12 34 GND 27 F0i 7 D0 13 33 F0i D0 26 D1 C4i 8 32 C4i 14 D1 A0 25 9 D2 A0 15 31 D2 A1 10 24 D3 A1 16 30 D3 A2 23 D4 11 A2 17 29 D4 (1) DNC 5703 drw03 DTA 40 1 5703 drw02 RX0 ODE 39 2 RX1 TX0 38 3 RX2 TX1 37 4 PQFP: 0.80mm pitch, 10mm x 10mm PLCC: 0.05in. pitch, 0.65in. x 0.65in. RX3 TX2 36 5 (DB44-1, order code: DB) (J44-1, order code: J) VCC TX3 6 35 TOP VIEW TOP VIEW (1) VCC DNC 7 34 (1) VCC DNC 8 33 (1) VCC DNC 9 32 (1) DNC VCC 10 31 GND F0i 11 30 D0 C4i 12 29 A0 D1 13 28 A1 D2 27 14 A2 15 26 D3 16 25 A3 D4 NOTE: A4 17 24 D5 1. DNC - Do Not Connect A5 18 23 D6 19 22 D7 DS 20 21 R/W CS 5703 drw04 PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in. (P40-1, order code: P) PIN DESCRIPTIONS TOP VIEW SYMBOL NAME I/O DESCRIPTION GND Ground. Ground Rail. VCC VCC +5.0 Volt Power Supply. DTA Data Acknowledgment O This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this (Open Drain) output. RX0-3 RX Input 0 to 3 I Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. F0i Frame Pulse I This input identifies frame synchronization signals formatted to ST-BUS specifications. C4i Clock I 4.096 MHz serial clock for shifting data in and out of the data streams. A0-A5 Address 0 to 5 I These lines provide the address to IDT728981 internal registers. DS Data Strobe I This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. R/W Read/Write I This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. CS Chip Select I Active LOW input enabling a microprocessor read or write of control register or internal memories. D0-D7 Data Bus 0 to 7 I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. TX0-3 TX Outputs 0 to 3 O Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. (Three-state Outputs) ODE Output Drive Enable I This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. 2 (1) 6 DNC (1) DNC 18 5 RX2 A3 19 4 RX1 A4 20 3 RX0 A5 21 2 DTA 22 DS (1) 1 DNC R/W 23 44 ODE CS 24 43 TX0 25 D7 42 TX1 D6 26 41 TX2 D5 27 (1) 40 DNC (1) DNC 28 (1) DNC 12 44 DNC(1) A3 13 43 RX2 14 42 RX1 A4 15 41 A5 RX0 16 40 DTA DS R/W 17 39 DNC(1) 18 38 CS ODE D7 19 37 TX0 D6 20 36 TX1 21 35 TX2 D5 (1) DNC 22 34 DNC(1)