TIME SLOT INTERCHANGE IDT728985 DIGITAL SWITCH 256 x 256 and write access to individual channels. As an important function of a digital switch is to maintain sequence integrity and minimize throughput delay, the 256 x 256 channel non-blocking switch IDT728985 is an ideal solution for most switching needs. Automatic signal identification (ST-BUS , GCI) 8 RX inputs 32 channels at 64 Kbit/s per serial line 8 TX outputs 32 channels at 64 Kbit/s per serial line Three-state serial outputs Frame sequence, constant throughput delay, and guaranteed minimum Microprocessor Interface (8-bit data bus) delay are high priority requirements in todays integrated data and multimedia Frame Integrity for data applications networks. The IDT728985 provides these functions on a per-channel basis 5V Power Supply using a standard microprocessor control interface. Each of the eight serial lines Operating Temperature Range -40C to +85C is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data. Available in 44-pin Plastic Leaded Chip Carrier (PLCC), In Processor Mode, the microprocessor can access the input and output time 44-pin Plastic Quad Flatpack (PQFP) and 40-pin Plastic Dip slots to control other devices such as ISDN transceivers and trunk interfaces. (P-DIP) Supporting both GCI and ST-BUS formats, IDT728985 has incorporated an internal circuit to automatically identify the polarity and format of the frame synchronization. The IDT728985 is a ST-BUS /GCI compatible digital switch controlled by A functional block diagram of the IDT728985 device is shown on page 1. a microprocessor. The IDT728985 can handle as many as 256, 64 Kbit/s input The serial streams operate continuously at 2.048 Mb/s and are arranged in and output channels. Those 256 channels are divided into 8 serial inputs and 125s wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and outputs, each of which consists of 32 channels. The IDT728985 provides per- channel variable or constant throughput delay modes and microprocessor read C4i F0i ODE VCC GND Timing TX0 RX0 Unit Output MUX TX1 RX1 TX2 RX2 Receive Transmit TX3 RX3 Data Serial Data Serial Data Memory Streams Streams RX4 TX4 RX5 Connection TX5 Control Register Memory RX6 TX6 RX7 Microprocessor Interface TX7 5708 drw01 CCO DS A0/ CS R/W D0/ DTA A5 D7 1 2001 Integrated Device Technology, Inc. DSC-5708/2IDT728985 Time Slot Interchange Commercial Temperature Range Digital Switch 256 x 256 INDEX INDEX RX3 1 33 TX3 RX3 7 39 TX3 RX4 2 32 TX4 RX4 8 38 TX4 TX5 RX5 3 31 9 37 RX5 TX5 RX6 4 30 TX6 RX6 10 36 TX6 RX7 5 29 TX7 35 RX7 11 TX7 VCC 6 28 GND VCC 12 34 GND CCO DTA 40 F0i 7 27 D0 1 13 33 D0 F0i 26 RX0 ODE 8 D1 2 39 C4i 32 C4i 14 D1 A0 9 25 RX1 TX0 D2 3 38 A0 15 31 D2 A1 10 24 D3 TX1 RX2 4 37 16 30 A1 D3 A2 11 23 D4 TX2 RX3 36 5 A2 17 29 D4 RX4 TX3 6 35 5708 drw03 RX5 TX4 7 34 5708 drw02 RX6 TX5 8 33 TX6 RX7 32 9 VCC TX7 31 10 PLCC: 0.05in. pitch, 0.65in. x 0.65in. F0i GND 11 30 PQFP: 0.80mm pitch, 10mm x 10mm (J44-1, order code: J) D0 C4i (DB44-1, order code: DB) 12 29 TOP VIEW A0 D1 TOP VIEW 13 28 A1 D2 27 14 A2 15 26 D3 25 A3 16 D4 24 A4 17 D5 A5 23 18 D6 19 22 D7 DS NOTE: 20 21 R/W CS 1. DNC - Do Not Connect 5708 drw04 PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in. (P40-1, order code: P) TOP VIEW SYMBOL NAME I/O DESCRIPTION GND Ground. Ground Rail. VCC VCC +5.0 Volt Power Supply. DTA Data Acknowledgment O This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at th is (Open Drain) output. RX0-7 RX Input 0 to 7 I Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. F0i Frame Pulse I This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS and GCI. C4i Clock I 4.096 MHz serial clock for shifting data in and out of the data streams. A0-A5 Address 0 to 5 I These lines provide the address to IDT728985 internal registers. DS Data Strobe I This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. R/W Read/Write I This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. CS Chip Select I Active LOW input enabling a microprocessor read or write of control register or internal memories. D0-D7 Data Bus 0 to 7 I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. TX0-7 TX Outputs 0 to 7 O Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. (Three-state Outputs) ODE Output Drive Enable I This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. CCO Control Channel Output O This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CCO bit in the Connection Memory HIGH locations. 2 (1) 6 DNC(1) DNC 18 5 RX2 A3 19 4 RX1 A4 20 3 RX0 A5 21 2 DTA 22 DS 1 CCO 23 R/W 44 ODE CS 24 43 TX0 25 D7 42 TX1 26 D6 41 TX2 D5 27 40 DNC(1) (1) DNC 28 (1) DNC 12 44 DNC(1) 13 43 RX2 A3 14 42 A4 RX1 15 41 A5 RX0 16 40 DS DTA 17 39 CCO R/W CS 18 38 ODE 19 37 D7 TX0 D6 20 36 TX1 D5 21 35 TX2 (1) 22 34 DNC DNC(1)