3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO 131,072 x 18 IDT72V295 IDT72V2105 262,144 x 18 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Select IDT Standard timing (using EF and FF flags) or First Word FEATURES: Fall Through timing (using OR and IR flags) Choose among the following memory organizations: Output enable puts data outputs into high impedance state IDT72V295 131,072 x 18 Easily expandable in depth and width IDT72V2105 262,144 x 18 Independent Read and Write clocks (permit reading and writing Pin-compatible with the IDT72V255/72V265 and the IDT72V275/ simultaneously) 72V285 SuperSync FIFOs Available in the 64-pin Thin Quad Flat Pack (TQFP) 10ns read/write cycle time (6.5ns access time) High-performance submicron CMOS technology Fixed, low first word data latency time Green parts available, see ordering information 5V input tolerant Auto power down minimizes standby power consumption DESCRIPTION: Master Reset clears entire FIFO The IDT72V295/72V2105 are exceptionally deep, high speed, CMOS Partial Reset clears data, but retains programmable settings First-In-First-Out (FIFO) memories with clocked read and write controls. These Retransmit operation with fixed, low first word data latency time FIFOs offer numerous improvements over previous SuperSync FIFOs, includ- Empty, Full and Half-Full flags signal FIFO status ing the following: Programmable Almost-Empty and Almost-Full flags, each flag can The limitation of the frequency of one clock input with respect to the other default to one of two preselected offsets has been removed. The Frequency Select pin (FS) has been removed, Program partial flags by either serial or parallel means FUNCTIONAL BLOCK DIAGRAM D0 -D17 WEN WCLK LD SEN INPUT REGISTER OFFSET REGISTER FF/IR PAF FLAG EF/OR WRITE CONTROL PAE LOGIC LOGIC HF RAM ARRAY FWFT/SI 131,072 x 18 WRITE POINTER 262,144 x 18 READ POINTER READ RT CONTROL LOGIC OUTPUT REGISTER MRS RESET RCLK LOGIC PRS REN 4668 drw 01 Q0 -Q17 OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4668/7IDT72V295/72V2105 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 131,072 x 18, 262,144 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES The input port is controlled by a Write Clock (WCLK) input and a Write DESCRIPTION (CONTINUED) Enable (WEN) input. Data is written into the FIFO on every rising edge of thus it is no longer necessary to select which of the two clock inputs, WCLK when WEN is asserted. The output port is controlled by a Read Clock RCLK or WCLK, is running at the higher frequency. (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on The period required by the retransmit operation is now fixed and short. every rising edge of RCLK when REN is asserted. An Output Enable (OE) The first word data latency period, from the time the first word is written input is provided for three-state control of the outputs. to an empty FIFO to the time it can be read, is now fixed and short. (The The frequencies of both the RCLK and the WCLK signals may vary from variable clock cycle counting delay associated with the latency period 0 to fMAX with complete independence. There are no restrictions on the found on previous SuperSync devices has been eliminated on this frequency of the one clock input with respect to the other. SuperSync family.) There are two possible timing modes of operation with these devices: SuperSync FIFOs are particularly appropriate for network, video, telecom- IDT Standard mode and First Word Fall Through (FWFT) mode. munications, data communications and other applications that need to buffer large amounts of data. PIN CONFIGURATIONS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 OE Q5 RT 50 31 Q4 51 30 VCC REN Q3 RCLK 52 29 53 28 Q2 EF/OR GND 54 27 PAE VCC Q1 55 26 HF 56 72V295 25 Q0 PAF GND 57 24 72V2105 FF/IR 58 23 D0 59 22 D1 GND FWFT/SI 60 21 D2 LD 61 20 D3 D4 MRS 62 19 D5 63 18 PRS WCLK 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4668 drw02 TQFP (PN64, order code: PF) TOP VIEW NOTE: 1. DC = Dont Care. Must be tied to GND or VCC, cannot be left open. 2 D6 WEN Q17 SEN Q16 (1) DC GND VCC Q15 GND Q14 D17 VCC D16 Q13 D15 Q12 D14 Q11 D13 GND D12 Q10 D11 Q9 D10 Q8 D9 Q7 D8 Q6 D7 GND