3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO 262,144 x 9 IDT72V2101 524,288 x 9 IDT72V2111 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Available in the 64-pin Thin Quad Flat Pack (TQFP) FEATURES: High-performance submicron CMOS technology Choose among the following memory organizations: Industrial temperature range (40C to +85C) is available IDT72V2101 262,144 x 9 Green parts available, see ordering information IDT72V2111 524,288 x 9 Pin-compatible with the IDT72V261/72V271 and the IDT72V281/ DESCRIPTION: 72V291 SuperSync FIFOs 10ns read/write cycle time (6.5ns access time) The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS Fixed, low first word data latency time First-In-First-Out (FIFO) memories with clocked read and write controls. These 5V input tolerant FIFOs offer numerous improvements over previous SuperSync FIFOs, Auto power down minimizes standby power consumption including the following: Master Reset clears entire FIFO The limitation of the frequency of one clock input with respect to the other has Partial Reset clears data, but retains programmable settings been removed. The Frequency Select pin (FS) has been removed, thus Retransmit operation with fixed, low first word data latency time it is no longer necessary to select which of the two clock inputs, RCLK or Empty, Full and Half-Full flags signal FIFO status WCLK, is running at the higher frequency. Programmable Almost-Empty and Almost-Full flags, each flag can The period required by the retransmit operation is now fixed and short. default to one of two preselected offsets The first word data latency period, from the time the first word is written to an Program partial flags by either serial or parallel means empty FIFO to the time it can be read, is now fixed and short. (The variable Select IDT Standard timing (using EF and FF flags) or First Word Fall clock cycle counting delay associated with the latency period found on Through timing (using OR and IR flags) previous SuperSync devices has been eliminated on this SuperSync family.) Output enable puts data outputs into high impedance state SuperSync FIFOs are particularly appropriate for network, video, telecommu- Easily expandable in depth and width nications, data communications and other applications that need to buffer large Independent Read and Write clocks (permit reading and writing amounts of data. simultaneously) FUNCTIONAL BLOCK DIAGRAM D0 -D8 WEN WCLK LD SEN INPUT REGISTER OFFSET REGISTER FF/IR PAF FLAG EF/OR WRITE CONTROL LOGIC PAE LOGIC HF RAM ARRAY FWFT/SI 262,144 x 9 524,288 x 9 WRITE POINTER READ POINTER READ CONTROL RT LOGIC OUTPUT REGISTER MRS RESET RCLK LOGIC PRS REN Q0 -Q8 4669 drw 01 OE IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. JANUARY 2018 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 DSC-4669/6 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.COMMERCIAL AND INDUSTRIAL IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 TEMPERATURE RANGES In FWFT mode, the first word written to an empty FIFO is clocked directly DESCRIPTION (CONTINUED) to the data output lines after three transitions of the RCLK signal. A REN The input port is controlled by a Write Clock (WCLK) input and a Write Enable does not have to be asserted for accessing the first word. However, (WEN) input. Data is written into the FIFO on every rising edge of WCLK when subsequent words written to the FIFO do require a LOW on REN for access. WEN is asserted. The output port is controlled by a Read Clock (RCLK) input The state of the FWFT/SI input during Master Reset determines the timing and Read Enable (REN) input. Data is read from the FIFO on every rising edge mode in use. of RCLK when REN is asserted. An Output Enable (OE) input is provided for For applications requiring more data storage capacity than a single FIFO three-state control of the outputs. can provide, the FWFT timing mode permits depth expansion by chaining The frequencies of both the RCLK and the WCLK signals may vary from FIFOs in series (i.e. the data outputs of one FIFO are connected to the 0 to fMAX with complete independence. There are no restrictions on the corresponding data inputs of the next). No external logic is required. frequency of the one clock input with respect to the other. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), There are two possible timing modes of operation with these devices: FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable IDT Standard mode and First Word Fall Through (FWFT) mode. Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and In IDT Standard mode, the first word written to an empty FIFO will not FF functions are selected in IDT Standard mode. The IR and OR functions are appear on the data output lines unless a specific read operation is selected in FWFT mode. HF, PAE and PAF are always available for use, performed. A read operation, which consists of activating REN and enabling a irrespective of timing mode. rising RCLK edge, will shift the word from internal memory to the data output lines. PIN CONFIGURATIONS PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (3) DNC 1 48 WEN (3) DNC SEN 2 47 (1) GND DC 3 46 (3) DNC VCC 4 45 (3) DNC VCC 5 44 (2) VCC GND 6 43 (3) (2) DNC GND 7 42 (3) (2) DNC GND 8 41 (3) (2) DNC GND 9 40 (2) GND GND 10 39 (3) (2) DNC GND 11 38 (3) (2) DNC GND 12 37 (2) GND Q8 13 36 (2) GND Q7 14 35 Q6 D8 15 34 D7 GND 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4669 drw 02 TQFP (PN64, order code: PF) TOP VIEW NOTES: 1. DC = Dont Care. Must be tied to GND or VCC, cannot be left open. 2. This pin may either be tied to ground or left open. 3. DNC = Do Not Connect. 2 WCLK D5 PRS D4 MRS D3 LD D2 FWFT/SI D1 GND D0 FF/IR GND PAF HF Q0 Q1 VCC GND PAE Q2 EF/OR Q3 RCLK VCC REN Q4 RT Q5 OE D6