3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO 131,072 x 18/262,144 x 9 IDT72V2103 262,144 x 18/524,288 x 9 IDT72V2113 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: Empty, Full and Half-Full flags signal FIFO status Choose among the following memory organizations: Programmable Almost-Empty and Almost-Full flags, each flag can IDT72V2103 131,072 x 18/262,144 x 9 default to one of eight preselected offsets IDT72V2113 262,144 x 18/524,288 x 9 Selectable synchronous/asynchronous timing modes for Almost- Functionally compatible with the IDT72V255LA/72V265LA and Empty and Almost-Full flags IDT72V275/72V285 SuperSync FIFOs Program programmable flags by either serial or parallel means Up to 166 MHz Operation of the Clocks Select IDT Standard timing (using EF and FF flags) or First Word User selectable Asynchronous read and/or write ports (BGA Only) Fall Through timing (using OR and IR flags) 6 ns read/write cycle time (4.0 ns access time) Output enable puts data outputs into high impedance state User selectable input and output port bus-sizing Easily expandable in depth and width - x9 in to x9 out JTAG port, provided for Boundary Scan function (BGA Only) - x9 in to x18 out Independent Read and Write Clocks (permit reading and writing - x18 in to x9 out simultaneously) - x18 in to x18 out Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball Big-Endian/Little-Endian user selectable byte representation Grid Array (BGA) (with additional features) 5V tolerant inputs Pin compatible to the SuperSync II (IDT72V223/72V233/72V243/ Fixed, low first word latency 72V253/72V263/72V273/72V283/72V293) family Zero latency retransmit High-performance submicron CMOS technology Auto power down minimizes standby power consumption Industrial temperature range (40C to +85C) is available Master Reset clears entire FIFO Green parts available, see ordering information Partial Reset clears data, but retains programmable settings FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x9 or x18) LD SEN *Available on the WEN WCLK/WR * BGA package only. INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE FLAG WRITE CONTROL ASYW HF LOGIC * LOGIC RAM ARRAY FWFT/SI PFM 131,072 x 18 or 262,144 x 9 FSEL0 262,144 x 18 or 524,288 x 9 FSEL1 WRITE POINTER READ POINTER BE CONTROL LOGIC IP RT READ CONTROL RM OUTPUT REGISTER LOGIC IW BUS ASYR * CONFIGURATION OW MRS RESET RCLK/RD LOGIC PRS * REN TCK * * TRST JTAG CONTROL * TMS (BOUNDARY 6119 drw01 * TDI Q0 -Qn (x9 or x18) SCAN) OE * TDO * IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-6119/17TM TM COMMERCIAL AND INDUSTRIAL IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II NARROW BUS FIFO IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II NARROW BUS FIFO 8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 TEMPERATURE RANGES The period required by the retransmit operation is now fixed and short. DESCRIPTION: The first word data latency period, from the time the first word is written to an The IDT72V2103/72V2113 are exceptionally deep, high speed, CMOS empty FIFO to the time it can be read, is now fixed and short. (The variable First-In-First-Out (FIFO) memories with clocked read and write controls and a clock cycle counting delay associated with the latency period found on flexible Bus-Matching x9/x18 data flow. These FIFOs offer numerous improve- previous SuperSync devices has been eliminated on this SuperSync family.) ments over previous SuperSync FIFOs, including the following: Asynchronous/Synchronous translation on the read or write ports. Flexible x9/x18 Bus-Matching on both read and write ports. High density offerings up to 4 Mbit. The limitation of the frequency of one clock input with respect to the other has Bus-Matching SuperSync FIFOs are particularly appropriate for network, been removed. The Frequency Select pin (FS) has been removed, thus it video, telecommunications, data communications and other applications that is no longer necessary to select which of the two clock inputs, RCLK or WCLK, need to buffer large amounts of data and match busses of unequal sizes. is running at the higher frequency. PIN CONFIGURATIONS INDEX WEN 1 60 RT SEN 2 59 OE (1) 3 58 DNC VCC VCC 4 57 Q17 (1) DNC 56 5 Q16 IW 55 6 GND GND 54 7 GND D17 8 53 Q15 VCC 9 52 Q14 D16 51 10 VCC D15 11 50 Q13 D14 12 49 Q12 D13 13 GND 48 GND 14 Q11 47 D12 15 46 GND D11 16 Q10 45 D10 17 VCC 44 D9 18 Q9 43 D8 19 Q8 42 VCC 20 41 Q7 6119 drw02 NOTE: 1. DNC = Do Not Connect. TQFP (PN80, order code: PF) TOP VIEW 2 21 D7 80 WCLK 22 D6 79 PRS 23 GND MRS 78 24 LD D5 77 25 D4 76 FWFT/SI D3 26 75 FF/IR D2 27 PAF 74 28 D1 OW 73 D0 29 FSEL0 72 GND 30 HF 71 Q0 31 FSEL1 70 32 BE Q1 69 33 GND IP 68 34 Q2 VCC 67 35 Q3 PAE 66 36 VCC PFM 65 Q4 37 EF/OR 64 Q5 38 RM 63 39 GND 62 RCLK 40 Q6 61 REN