3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO 512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9 IDT72V223, IDT72V233 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9 IDT72V243, IDT72V253 8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9 IDT72V263, IDT72V273 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9 IDT72V283, IDT72V293 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Zero latency retransmit FEATURES: Auto power down minimizes standby power consumption Choose among the following memory organizations: Master Reset clears entire FIFO IDT72V223 512 x 18/1,024 x 9 Partial Reset clears data, but retains programmable settings IDT72V233 1,024 x 18/2,048 x 9 Empty, Full and Half-Full flags signal FIFO status IDT72V243 2,048 x 18/4,096 x 9 Programmable Almost-Empty and Almost-Full flags, each flag can IDT72V253 4,096 x 18/8,192 x 9 default to one of eight preselected offsets IDT72V263 8,192 x 18/16,384 x 9 IDT72V273 16,384 x 18/32,768 x 9 Selectable synchronous/asynchronous timing modes for Almost- IDT72V283 32,768 x 18/65,536 x 9 Empty and Almost-Full flags IDT72V293 65,536 x 18/131,072 x 9 Program programmable flags by either serial or parallel means Functionally compatible with the IDT72V255LA/72V265LA and Select IDT Standard timing (using EF and FF flags) or First Word IDT72V275/72V285 SuperSync FIFOs Fall Through timing (using OR and IR flags) Up to 166 MHz Operation of the Clocks Output enable puts data outputs into high impedance state User selectable Asynchronous read and/or write ports (BGA Only) Easily expandable in depth and width User selectable input and output port bus-sizing JTAG port, provided for Boundary Scan function (BGA Only) - x9 in to x9 out Independent Read and Write Clocks (permit reading and writing - x9 in to x18 out simultaneously) - x18 in to x9 out Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball - x18 in to x18 out Grid Array (BGA) (with additional features) Pin to Pin compatible to the higher density of IDT72V2103/72V2113 High-performance submicron CMOS technology Big-Endian/Little-Endian user selectable byte representation Industrial temperature range (40C to +85C) is available 5V tolerant inputs Green parts available, see ordering information Fixed, low first word latency FUNCTIONAL BLOCK DIAGRAM *Available on the D0 -Dn (x9 or x18) LD SEN BGA package only. WEN WCLK/WR * INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE FLAG WRITE CONTROL ASYW RAM ARRAY LOGIC HF * LOGIC 512 x 18 or 1,024 x 9 FWFT/SI 1,024 x 18 or 2,048 x 9 PFM 2,048 x 18 or 4,096 x 9 FSEL0 4,096 x 18 or 8,192 x 9 FSEL1 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 WRITE POINTER READ POINTER 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 BE CONTROL LOGIC IP RT READ CONTROL RM LOGIC OUTPUT REGISTER IW BUS ASYR * CONFIGURATION OW MRS RESET RCLK/RD LOGIC PRS * REN TCK * * TRST JTAG CONTROL * TMS (BOUNDARY SCAN) 4666 drw01 * TDI Q0 -Qn (x9 or x18) OE * TDO * IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. MARCH 2018 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4666/18TM IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II NARROW BUS FIFO COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 The period required by the retransmit operation is now fixed and short. DESCRIPTION: The first word data latency period, from the time the first word is written to an The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ empty FIFO to the time it can be read, is now fixed and short. (The variable 72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) clock cycle counting delay associated with the latency period found on memories with clocked read and write controls and a flexible Bus-Matching x9/ previous SuperSync devices has been eliminated on this SuperSync family.) x18 data flow. These FIFOs offer numerous improvements over previous Asynchronous/Synchronous translation on the read or write ports SuperSync FIFOs, including the following: High density offerings up to 1 Mbit Flexible x9/x18 Bus-Matching on both read and write ports Bus-Matching SuperSync FIFOs are particularly appropriate for network, The limitation of the frequency of one clock input with respect to the other video, telecommunications, data communications and other applications that has been removed. The Frequency Select pin (FS) has been removed, need to buffer large amounts of data and match busses of unequal sizes. thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. PIN CONFIGURATIONS INDEX WEN 1 60 RT 2 59 SEN OE (1) 3 58 DNC VCC VCC 57 4 Q17 (1) DNC 56 5 Q16 55 IW 6 GND GND 54 7 GND D17 8 53 Q15 VCC 9 52 Q14 D16 10 51 VCC D15 50 11 Q13 D14 12 49 Q12 D13 13 48 GND GND 14 47 Q11 D12 15 46 GND D11 16 45 Q10 D10 17 44 VCC D9 18 Q9 43 D8 19 Q8 42 VCC 20 Q7 41 4666 drw02 TQFP (PN80, order code: PF) NOTE: TOP VIEW 1. DNC = Do Not Connect. 2 21 D7 80 WCLK 22 D6 79 PRS 23 GND 78 MRS 24 LD D5 77 25 D4 76 FWFT/SI D3 FF/IR 26 75 D2 27 PAF 74 28 D1 OW 73 29 D0 FSEL0 72 GND HF 30 71 Q0 31 FSEL1 70 Q1 32 BE 69 33 GND IP 68 34 Q2 VCC 67 Q3 35 PAE 66 VCC 36 PFM 65 Q4 37 EF/OR 64 Q5 38 63 RM GND 39 62 RCLK Q6 40 REN 61