TM 3.3 VOLT CMOS SyncBiFIFO 72V3612 64 x 36 x 2 Passive parity checking on each port FEATURES: Parity generation can be selected for each port Two independent clocked FIFOs (64 x 36 storage capacity each) Available in space saving 120-pin thin quad flat package (TQFP) buffering data in opposite directions Green parts available, see ordering information Supports clock frequencies up to 83 MHz Fast access times of 8ns DESCRIPTION: Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a The IDT72V3612 is designed to run off a 3.3V supply for exceptionally low- single clock edge is permitted) power consumption. This device is a monolithic high-speed, low-power CMOS Mailbox bypass Register for each FIFO bi-directional clocked FIFO memory. It supports clock frequencies up to 83 MHz Programmable Almost-Full and Almost-Empty Flags and has read access times as fast as 8ns. The FIFO operates in IDT Standard Microprocessor interface control logic mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip EFA , FFA , AEA , and AFA flags synchronized by CLKA buffer data in opposite directions. Each FIFO has flags to indicate empty and EFB , FFB , AEB , and AFB flags synchronized by CLKB full conditions and two programmable flags (Almost-Full and Almost-Empty) to FUNCTIONAL BLOCK DIAGRAM CLKA CSA Port-A MBF1 W/RA Control ENA Logic MBA Parity PEFB Gen/Check Mail 1 Register PGB RAM 36 ARRAY RST 64 x 36 Device Control ODD/ EVEN Read Write Pointer Pointer EFB FFA Status Flag Logic AEB AFA FIFO1 36 FS0 Programmable Flag B0 - B36 Offset Register FS1 A0 - A35 FIFO2 FFB EFA Status Flag Logic AEA AFB Read Write 36 Pointer Pointer RAM ARRAY 64 x 36 PGA Mail 2 Register Parity Gen/Check PEFA CLKB Port-B CSB Control W/RB MBF2 Logic ENB MBB 4659 drw 01 COMMERCIAL TEMPERATURE RANGE 11 Feb.19.20 Input Register Output Register Parity Generation Parity Generation Output Register Input RegisterTM 72V3612 3.3V, CMOS SyncBiFIFO 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE indicate when a selected number of words is stored in memory. Communication are independent of one another and can be asynchronous or coincident. The between each port can bypass the FIFOs via two 36-bit mailbox registers. Each enables for each port are arranged to provide a simple bi-directional interface mailbox register has a flag to signal when new mail has been stored. Parity is between microprocessors and/or buses with synchronous control. checked passively on each port and may be ignored if not desired. Parity The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO are generation can be selected for data read from each port. Two or more devices two-stage synchronized to the port clock that writes data to its array. The Empty can be used in parallel to create wider data paths. Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage This device is a clocked FIFO, which means each port employs a synchronized to the port clock that reads data from its array. synchronous interface. All data transfers through a port are gated to the LOW- The IDT72V3612 is characterized for operation from 0C to 70C. This to-HIGH transition of a port clock by enable signals. The clocks for each port device is fabricated using high speed, submicron CMOS technology. PIN CONFIGURATION FFB B23 91 60 B24 CSB 92 59 B25 ENB 93 58 B26 94 CLKB 57 W/RB VCC 95 56 B27 96 55 VCC B28 54 PGB 97 PEFB B29 98 53 MBF1 GND 99 52 100 B30 51 MBB 101 B31 50 NC B32 102 NC 49 B33 103 48 NC B34 104 NC 47 B35 105 GND 46 GND 106 RST 45 A35 107 72V3612 ODD/EVEN 44 A34 108 43 FS0 A33 109 FS1 42 A32 110 MBA 41 A31 111 40 MBF2 A30 112 39 PEFA GND 113 38 PGA A29 114 VCC 37 A28 115 36 W/RA A27 116 35 CLKA VCC 117 34 ENA A26 118 33 CSA A25 119 32 FFA A24 120 31 AFA 4659 drw03 NOTES: 1. Pin 1 identifier in corner. 2. NC - No internal connection. TQFP (PNG120, order code: PFG) TOP VIEW 2 Feb.19.20 A23 B22 1 90 A22 B21 2 89 A21 3 GND 88 GND B20 4 87 A20 5 B19 86 A19 6 85 B18 A18 7 B17 84 A17 8 B16 83 A16 B15 9 82 A15 10 B14 81 A14 11 80 B13 A13 12 B12 79 A12 13 78 B11 A11 14 77 B10 A10 15 GND 76 GND 16 75 B9 A9 17 B8 74 A8 18 73 B7 A7 19 72 VCC VCC 20 71 B6 21 A6 70 B5 A5 22 B4 69 A4 23 68 B3 A3 24 67 GND GND 25 66 B2 26 A2 65 B1 A1 27 64 B0 28 A0 63 EFB EFA 29 AEB 62 AEA AFB 30 61