3.3V HIGH-DENSITY SUPERSYNC II 36-BIT FIFO IDT72V3640, IDT72V3650 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 IDT72V3660, IDT72V3670 IDT72V3680, IDT72V3690 16,384 x 36, 32,768 x 36 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Zero latency retransmit FEATURES: Auto power down minimizes standby power consumption Choose among the following memory organizations:Commercial Master Reset clears entire FIFO IDT72V3640 1,024 x 36 Partial Reset clears data, but retains programmable settings IDT72V3650 2,048 x 36 Empty, Full and Half-Full flags signal FIFO status IDT72V3660 4,096 x 36 Programmable Almost-Empty and Almost-Full flags, each flag can IDT72V3670 8,192 x 36 default to one of eight preselected offsets IDT72V3680 16,384 x 36 Selectable synchronous/asynchronous timing modes for Almost- IDT72V3690 32,768 x 36 Empty and Almost-Full flags Up to 166 MHz Operation of the Clocks Program programmable flags by either serial or parallel means User selectable Asynchronous read and/or write ports (PBGA Only) Select IDT Standard timing (using EF and FF flags) or First Word User selectable input and output port bus-sizing Fall Through timing (using OR and IR flags) - x36 in to x36 out Output enable puts data outputs into high impedance state - x36 in to x18 out Easily expandable in depth and width - x36 in to x9 out JTAG port, provided for Boundary Scan function (PBGA Only) - x18 in to x36 out Independent Read and Write Clocks (permit reading and writing - x9 in to x36 out simultaneously) Pin to Pin compatible to the higher density of IDT72V36100 and Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic IDT72V36110 Ball Grid Array (PBGA) (with additional features) Big-Endian/Little-Endian user selectable byte representation High-performance submicron CMOS technology 5V input tolerant Industrial temperature range (40C to +85C) is available Fixed, low first word latency Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM *Available on the PBGA package only. D0 -Dn (x36, x18 or x9) LD SEN WEN WCLK/WR * INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR FLAG PAE WRITE CONTROL ASYW HF LOGIC * LOGIC FWFT/SI PFM RAM ARRAY FSEL0 1,024 x 36, 2,048 x 36 FSEL1 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 WRITE POINTER READ POINTER BE CONTROL LOGIC IP RT READ CONTROL RM BM OUTPUT REGISTER BUS LOGIC ASYR IW * CONFIGURATION OW MRS RESET RCLK/RD LOGIC PRS * REN TCK * * TRST JTAG CONTROL * TMS (BOUNDARY SCAN) 4667 drw01 * TDI Q0 -Qn (x36, x18 or x9) OE *TDO * IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AUGUST 2018 1 DSC-4667/19TM IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO COMMERCIAL AND INDUSTRIAL 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 TEMPERATURE RANGES Bus-Matching Sync FIFOs are particularly appropriate for network, video, DESCRIPTION: telecommunications, data communications and other applications that need to The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 are buffer large amounts of data and match busses of unequal sizes. exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories Each FIFO has a data input port (Dn) and a data output port (Qn), both of with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the data flow. These FIFOs offer several key user benefits: state of external control pins Input Width (IW), Output Width (OW), and Bus- Flexible x36/x18/x9 Bus-Matching on both read and write ports Matching (BM) pin during the Master Reset cycle. The period required by the retransmit operation is fixed and short. The input port can be selected as either a Synchronous (clocked) interface, The first word data latency period, from the time the first word is written to an or Asynchronous interface. During Synchronous operation the input port is empty FIFO to the time it can be read, is fixed and short. controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data Asynchronous/Synchronous translation on the read or write ports present on the Dn data inputs is written into the FIFO on every rising edge of High density offerings up to 1 Mbit PIN CONFIGURATIONS INDEX WEN OE 1 102 VCC 2 SEN 101 (1) VCC 3 100 DNC Q35 VCC 4 99 Q34 (1) 98 5 DNC Q33 97 IW 6 96 Q32 D35 7 95 GND D34 8 94 GND D33 9 Q31 93 D32 10 Q30 VCC 92 11 91 Q29 D31 12 90 Q28 D30 13 GND 89 Q27 14 Q26 D29 88 15 D28 87 VCC 16 86 Q25 D27 17 D26 18 85 Q24 GND D25 84 19 GND D24 20 83 82 Q23 D23 21 81 Q22 GND 22 D22 80 Q21 23 Q20 VCC 79 24 Q19 D21 25 78 77 Q18 D20 26 76 GND D19 27 Q17 75 D18 28 Q16 GND 29 74 VCC D17 30 73 VCC D16 31 72 32 71 Q15 D15 Q14 33 70 D14 Q13 D13 34 69 Q12 VCC 35 68 67 GND D12 36 37 66 Q11 GND 65 Q10 D11 38 4667 drw02a TQFP (PK128, order code: PF) NOTE: TOP VIEW 1. DNC = Do Not Connect. 2 D10 39 128 WCLK 127 D9 40 PRS 126 D8 41 MRS D7 125 42 LD D6 124 43 FWFT/SI 123 GND 44 FF/IR D5 122 VCC 45 121 D4 46 PAF D3 120 GND 47 VCC 48 119 OW D2 49 118 FS0 D1 50 117 HF D0 116 51 GND GND 115 FS1 52 Q0 114 53 BE Q1 113 IP 54 Q2 BM 55 112 Q3 56 111 VCC Q4 110 57 PAE Q5 109 58 PFM GND 59 108 EF/OR 107 Q6 60 RM VCC 106 GND 61 Q7 62 105 RCLK 104 Q8 63 REN 64 103 Q9 RT