3.3 VOLT TIME SLOT INTERCHANGE IDT72V70200 DIGITAL SWITCH 512 x 512 100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack FEATURES: (PQFP) and 100-pin Thin Quad Flatpack (TQFP) 512 x 512 channel non-blocking switching at 2.048 Mb/s 3.3V Power Supply Per-channel variable or constant throughput delay Operating Temperature Range -40C to +85C Automatic identification of ST-BUS /GCI interfaces Accept 16 serial data streams of 2.048 Mb/s DESCRIPTION: Automatic frame offset delay measurement Per-stream frame delay offset programming The IDT72V70200 is a non-blocking digital switch that has a capacity of Per-channel high impedance output control 512 x 512 channels at 2.048 Mb/s. Some of the main features are: program- Per-channel Processor Mode mable stream and channel control, Processor Mode, input offset delay and high- Control interface compatible to Intel/Motorola CPUs impedance output control. Connection memory block programming Per-stream input delay control is provided for managing large multi-chip IEEE-1149.1 (JTAG) Test Port switches that transport both voice channel and concatenated data channels. In Available in 84-pin Plastic Leaded Chip Carrier (PLCC), addition, input streams can be individually calibrated for input frame offset. FUNCTIONAL BLOCK DIAGRAM VCC GND RESET TMS TDI TDO TCK TRST IC ODE Test Port RX0 TX0 RX1 TX1 RX2 Loopback TX2 RX3 TX3 RX4 TX4 Receive RX5 Transmit TX5 Output Serial Data RX6 Serial Data TX6 MUX Streams RX7 Data Memory Streams TX7 RX8 TX8 RX9 TX9 RX10 TX10 RX11 TX11 Connection RX12 TX12 Internal Memory RX13 TX13 Registers RX14 TX14 RX15 TX15 Timing Unit Microprocessor Interface DS/ CLK F0i FE IC AS/ IM R/W / A0-A7 DTA CCO CS D8-D15/ RD ALE WR AD0-AD7 5711 drw01 AUGUST 2001 IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5711/3IDT72V70200 3.3V TIME SLOT INTERCHANGE COMMERCIAL TEMPERATURE RANGE DIGITAL SWITCH 512 x 512 PIN CONFIGURATIONS A1 BALL PAD CORNER A RX0 TX13 TX11 TX10 TX8 TX7 TX4 TX3 TX0 CCO B RX2 RX1 TX14 TX12 TX9 TX6 TX5 TX2 ODE D14 C RX5 RX4 RX3 TX15 VCC VCC DNC TX1 D15 D12 D RX7 RX8 RX6 VCC GND GND VCC DTA D13 D11 E RX10 RX9 VCC GND GND GND GND VCC D10 D9 F RX11 RX12 VCC GND VCC GND GND GND AD7 D8 G RX13 RX15 CLK VCC GND GND VCC AD4 AD6 AD5 H RX14 FE TCK RESET VCC VCC CS AD1 AD2 AD3 J F0i TRST TDI A0 A1 A4 A7 R/W /RW IM AD0 K TMS TDO IC IC A2 A3 A5 A6 DS/RD AS/ALE 1 2 3 4 5 6 7 8 9 10 5711 drw02 BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC) TOP VIEW INDEX 11 10 9 8 7 6 5 4 3 2 84 83 82 81 80 79 78 77 76 75 1 RX0 CCO 12 74 RX1 DTA 13 73 RX2 D15 14 72 RX3 D14 15 71 RX4 D13 16 70 RX5 D12 17 69 RX6 18 68 D11 RX7 19 67 D10 RX8 20 66 D9 RX9 21 65 D8 RX10 22 GND 64 RX11 23 VCC 63 RX12 24 AD7 62 RX13 25 AD6 61 RX14 26 AD5 60 RX15 27 59 AD4 F0i 28 58 AD3 FE 29 57 AD2 GND 30 56 AD1 CLK 31 AD0 55 VCC 32 GND 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 5711 drw03 NOTES: PLCC: 0.05in. pitch, 1.15in. x 1.15in. (PL84-1, order code: J) 1. DNC - Do Not Connect TOP VIEW 2. IC - Internal Connection, tie to GROUND for normal operation. 3. All I/O pins are 5V tolerant except for TMS, TDI and TRST. 2 GND TMS TX15 TDI TX14 TDO TX13 TCK TX12 TRST TX11 IC RESET TX10 IC TX9 A0 TX8 A1 VCC A2 GND A3 TX7 A4 TX6 A5 TX5 TX4 A6 TX3 A7 TX2 DS/RD TX1 R/W /RW CS TX0 AS/ALE ODE IM GND