IDT72V805
3.3 VOLT CMOS DUAL SyncFIFO
IDT72V815
DUAL 256 x 18, DUAL 512 x 18,
IDT72V825
DUAL 1,024 x 18, DUAL 2,048 x 18
IDT72V835
and DUAL 4,096 x 18
IDT72V845
Easily expandable in depth and width
FEATURES:
Asynchronous or coincident Read and Write Clocks
The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs
Asynchronous or synchronous programmable Almost-Empty
The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs
and Almost-Full flags with default settings
The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs
Half-Full flag capability
The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs
Output enable puts output data bus in high-impedance state
The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs
High-performance submicron CMOS technology
Offers optimal combination of large capacity (8K), high speed,
Available in a 128-pin thin quad flatpack (TQFP)
design flexibility, and small footprint
Industrial temperature range (40C to +85C) is available
Ideal for the following applications:
Green parts available, see ordering information
Network switching
Two level prioritization of parallel data
DESCRIPTION:
Bidirectional data transfer
Bus-matching between 18-bit and 36-bit data paths The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide
Width expansion to 36-bit per package synchronous (clocked) First-in, First-out (FIFO) memories designed to run
Depth expansion to 8,192 words per package off a 3.3V supply for exceptionally low power consumption. One dual
10 ns read/write cycle time IDT72V805/72V815/72V825/72V835/72V845 device is functionally equiva-
5V input tolerant lent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single
IDT Standard or First Word Fall Through timing package with all associated control, data, and flag lines assigned to
Single or double register-buffered Empty and Full Flags independent pins. These devices are very high-speed, low-power First-In,
FUNCTIONAL BLOCK DIAGRAM
HFA/(WXOA)
FFA/IRA
PAEA
EFA/
ORA
WCLKA
WCLKB
DA0-DA17
WENA LDA WENB DB0-DB17 LDB
PAFA
INPUT OFFSET
INPUT OFFSET
REGISTER REGISTER
REGISTER REGISTER
FFB/IRB
FLAG
PAFB
WRITE
FLAG
LOGIC
WRITE
EFB/ORB
CONTROL RAM
LOGIC
CONTROL
ARRAY RAM PAEB
LOGIC
LOGIC ARRAY
256 x 18 HFB/(WXOB)
512 x 18 256 x 18
512 x 18
1,024 x 18 READ
WRITE 2,048 x 18 1,024 x 18
POINTER
READ
WRITE 2,048 x 18
4,096 x 18
POINTER
POINTER
POINTER 4,096 x 18
FLA READ
READ
CONTROL
WXIA
EXPANSION CONTROL
LOGIC
(HFA)/WXOA
LOGIC LOGIC
EXPANSION
RXIA OUTPUT
LOGIC
OUTPUT
REGISTER
RXOA
REGISTER
RESET
RSA
LOGIC RESET
LOGIC
RSB RCLKB
RCLKA
OEB
QA0-QA17
RENB
OEA RENA RXOB
QB0-QB17
RXIB
(HFB)/WXOB
WXIB
4295 drw 01
FLB
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEBRUARY 2009
1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4295/4IDT72V805/72V815/72V825/72V835/72V845 COMMERCIAL AND INDUSTRIAL
3.3 V CMOS DUAL SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 TEMPERATURE RANGES
by asserting the Load pin (LD). A Half-Full flag (HF) is available for each FIFO
DESCRIPTION (CONTINUED)
that is implemented as a single device.
First-Out (FIFO) memories with clocked read and write controls. These FIFOs
There are two possible timing modes of operation with these devices:
are applicable for a wide variety of data buffering needs, such as optical disk
IDT Standard mode and First Word Fall Through (FWFT) mode.
controllers, Local Area Networks (LANs), and interprocessor communication.
In IDT Standard Mode, the first word written to an empty FIFO will not
Each of the two FIFOs contained in these devices has an 18-bit input and
appear on the data output lines unless a specific read operation is
output port. Each input port is controlled by a free-running clock (WCLK), and
performed. A read operation, which consists of activating REN and
an input enable pin (WEN). Data is read into the synchronous FIFO on every
enabling a rising RCLK edge, will shift the word from internal memory to the
clock when WEN is asserted. The output port of each FIFO bank is controlled
data output lines.
by another clock pin (RCLK) and another enable pin (REN). The Read Clock
In FWFT mode, the first word written to an empty FIFO is clocked directly
can be tied to the Write Clock for single clock operation or the two clocks can
to the data output lines after three transitions of the RCLK signal. A REN
run asynchronous of one another for dual-clock operation. An Output Enable
does not have to be asserted for accessing the first word.
pin (OE) is provided on the read port of each FIFO for three-state control of
These devices are depth expandable using a Daisy-Chain technique or
the output.
First Word Fall Through (FWFT) mode. The XI and XO pins are used to
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
expand the FIFOs. In depth expansion configuration, FL is grounded on
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
the first device and set to HIGH for all other devices in the Daisy Chain.
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using
programmable flags is controlled by a simple state machine, and is initiated
IDTs high-speed submicron CMOS technology.
PIN CONFIGURATIONS
INDEX
VCC LDA
1 102
PAFA OEA
2 101
RXIA
100 RSA
3
FFA VCC
4 99
WXOA/HFA 98
5 GND
RXOA
97 EFA
6
QA0 96 QA17
7
95
QA1 QA16
8
GND 94 GND
9
93
QA2 10 QA15
QA3 92 VCC
11
VCC 91 QA14
12
90
QA4 13 QA13
GND 89 GND
14
88
QA5 15 QA12
QA6 87 QA11
16
86 VCC
QA7 17
85
QA8 18 QA10
GND 84 QA9
19
83 DB8
DB7 20
82 DB9
DB6 21
81 DB10
DB5 22
80
DB4 23 DB11
79 DB12
DB3 24
78 DB13
DB2 25
77
DB14
DB1 26
76 DB15
DB0 27
PAEB 28 75 DB16
74 DB17
FLB 29
73 GND
WCLKB 30
RCLKB
31 72
WENB
71 RENB
WXIB 32
LDB
33 70
VCC
69 OEB
PAFB 34
68 RSB
RXIB 35
36 67 VCC
FFB
66 GND
37
WXOB/HFB
EFB
38 65
RXOB
4295 drw 02
TQFP (PK128-1, ORDER CODE: PF)
TOP VIEW
2 FEBRUARY 11, 2009
QB0 39 128 WXIA
QB1 40 127 WENA
GND 41 126 WCLKA
42 125 FLA
QB2
43 PAEA
QB3 124
VCC 44 123 DA0
DA1
QB4 45 122
DA2
GND 46 121
47 DA3
QB5 120
DA4
QB6 48 119
49 118 DA5
QB7
50
QB8 117 DA6
116 DA7
GND 51
DA8
QB9 52 115
DA9
114
QB10 53
DA10
VCC 54 113
DA11
55 112
QB11
DA12
QB12 56 111
DA13
57 110
GND
DA14
109
QB13 58
DA15
QB14 59 108
DA16
107
VCC 60
DA17
61 106
QB15
GND
62 105
GND
RCLKA
104
QB16 63
RENA
64 103
QB17