CY7C4201V/4211VCY7C4241V/4251VLow Voltage 256/512 9 Synchronous FIFOs CY7C4201V/4211V Low Voltage 256/512 9 Synchronous FIFOs Low Voltage 256/512 9 Synchronous FIFOs Features Functional Description High-speed, low-power, first-in, first-out (FIFO) memories The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. 256 9 (CY7C4201V) Programmable features include Almost Full/Almost Empty flags. 512 9 (CY7C4211V) These FIFOs provide solutions for a wide variety of data High-speed 66-MHz operation (15-ns read/write cycle time) buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. Low power (I = 20 mA) CC These FIFOs have 9-bit input and output ports that are controlled 3.3 V operation for low power consumption and easy integration by separate clock and enable signals. The input port is controlled into low-voltage systems by a Free-Running Clock (WCLK) and two Write Enable pins (WEN1, WEN2/LD). 5V-tolerant inputs V = 5 V IH(max) When WEN1 is LOW and WEN2/LD is HIGH, data is written into Fully asynchronous and simultaneous read and write operation the FIFO on the rising edge of the WCLK signal. While WEN1, Empty, full, and programmable almost empty and almost full WEN2/LD is held active, data is continually written into the FIFO status flags on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and two Read TTL compatible Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an Output Enable Pin (OE). The Read (RCLK) and Write (WCLK) Output Enable (OE) pin clocks may be tied together for single clock operation or the two Independent read and write enable pins clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable. Center power and ground pins for reduced noise Depth expansion is possible using one enable input for system Width expansion capability control, while the other enable is controlled by expansion logic to direct the flow of data. Space saving 32-pin 7 mm 7 mm TQFP For a complete list of related documentation, click here. 32-pin PLCC available in Pb-free Packages Logic Block Diagram Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06010 Rev. *I Revised November 18, 2015 CY7C4201V/4211V Contents Pin Configuration .............................................................3 Switching Characteristics .............................................. 10 Pin Definitions ..................................................................3 Switching Waveforms .................................................... 11 Selection Guide ................................................................4 Ordering Information ...................................................... 19 Architecture ......................................................................4 Ordering Code Definitions ......................................... 19 Functional Overview ........................................................4 Package Diagrams .......................................................... 20 Resetting the FIFO ......................................................4 Acronyms ........................................................................21 FIFO Operation ...........................................................4 Document Conventions ................................................. 21 Programming ...............................................................5 Units of Measure ....................................................... 21 Width Expansion Configuration ...................................7 Document History Page ................................................. 22 Flag Operation .............................................................7 Sales, Solutions, and Legal Information ...................... 23 Maximum Ratings .............................................................8 Worldwide Sales and Design Support ....................... 23 Operating Range ...............................................................8 Products ....................................................................23 Electrical Characteristics .................................................8 PSoC Solutions ...................................................... 23 Capacitance ......................................................................9 Cypress Developer Community ................................. 23 AC Test Loads and Waveforms .......................................9 Technical Support ..................................................... 23 Document Number: 38-06010 Rev. *I Page 2 of 23