IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT IDT74ALVCH16260
MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES: DESCRIPTION:
0.5 MICRON CMOS Technology
This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual
Typical tSK(o) (Output Skew) < 250ps
metal CMOS technology. The ALVCH16260 is used in applications in which
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
two separate data paths must be multiplexed onto, or demultiplexed from, a
machine model (C = 200pF, R = 0)
single data path. Typical applications include multiplexing and/or demultiplexing
VCC = 3.3V 0.3V, Normal Range
address and data information in microprocessor or bus-interface applications.
VCC = 2.7V to 3.6V, Extended Range
This device also is useful in memory interleaving applications.
VCC = 2.5V 0.2V
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
CMOS power levels (0.4 W typ. static)
for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA)
Rail-to-Rail output swing for increased noise margin
inputs control the bus transceiver functions. The OE1B and OE2B control
Available in TSSOP package
signals also allow bank control in the A-to-B direction. Address and/or data
information can be stored using the internal storage latches. The latch-enable
DRIVE FEATURES:
(LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage.
High Output Drivers: 24mA When the latch-enable input is high, the latch is transparent. When the latch-
Suitable for heavy loads enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The ALVCH16260 has been designed with a 24mA output driver. This
APPLICATIONS:
driver is capable of driving a moderate to heavy load while maintaining speed
3.3V high speed systems
performance.
3.3V and lower voltage computing systems
The ALVCH16260 has bus-hold which retains the inputs last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
29
OE1B
30
A-1B
LEA1B
1B1:12
12
LATCH
2
LE1B 1B-A
12
LATCH
12
12
28
SEL
1
OEA
1
M
A1:12
U
12
X
0
12
12 2B-A
27
LATCH
12
LE2B
A-2B
2B1:12
55
LATCH 12
LEA2B
56
OE2B
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE JULY 2009
1
2009 Integrated Device Technology, Inc. DSC-4737/6IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
(1)
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Symbol Description Max Unit
(2)
VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V
(3)
1 56 VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V
OEA OE2B
TSTG Storage Temperature 65 to +150 C
2
LE1B 55 LEA2B
IOUT DC Output Current 50 to +50 mA
2B3 3 54 2B4
IIK Continuous Clamp Current, 50 mA
GND
GND 4 53
VI < 0 or VI > VCC
5
2B2 52 2B5
IOK Continuous Clamp Current, VO < 0 50 mA
6
2B1
51 2B6
ICC Continuous Current through each 100 mA
ISS VCC or GND
VCC 7
50 VCC
NOTES:
A1 8 49 2B7
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
9 48 permanent damage to the device. This is a stress rating only and functional operation
A2 2B8
of the device at these or any other conditions above those indicated in the operational
10
A3 47 2B9
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
11 46 GND
GND
2. VCC terminals.
A4 12
45 2B10 3. All terminals except VCC.
A5 13 2B11
44
14 2B12
A6 43
CAPACITANCE (TA = +25C, F = 1.0MHz)
A7 15 42 1B12 (1)
Symbol Parameter Conditions Typ. Max. Unit
A8 16
41 1B11
CIN Input Capacitance VIN = 0V 5 7 pF
A9
17 40 1B10
COUT Output Capacitance VOUT = 0V 7 9 pF
18 CI/O I/O Port Capacitance VIN = 0V 7 9 pF
GND 39 GND
NOTE:
19 38 1B9
A10
1. As applicable to the device type.
A11
20 37 1B8
A12 36 1B7
21
22
VCC 35 VCC
1B1 23
34 1B6
1B2 24 1B5
33
25 GND
GND 32
(1)
FUNCTION TABLES
26
1B3 31 1B4
B-TO-A (OEB = H)
27 LEA1B
LE2B 30
SEL 28
29 OE1B Inputs Output
1Bx 2Bx SEL LE1B LE2B OEA Ax
HX H H X L H
TSSOP
TOP VIEW
LX H H X L L
(2)
XX H L X L A
0
XH L X H L H
XL L X H L L
(2)
XX L X L L A
0
XX XX X H Z
2