IDT74FCT16543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE FAST CMOS IDT74FCT16543AT/CT 16-BIT LATCHED TRANSCEIVER FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT16543T 16-bit latched transceivers are built using advanced High-speed, low-power CMOS replacement for ABT functions dual metal CMOS technology. These high-speed, low-power devices are Typical tSK(o) (Output Skew) < 250ps organized as two independent 8-bit D-type latched transceivers with Low input and output leakage 1A (max.) separate input and output control to permit independent control of data flow VCC = 5V 10% in either direction. For example, the A-to-B Enable (xCEAB) must be low High drive outputs (32mA IOH, 64mA IOL) in order to enter data from the A port or to output data from the B port. xLEAB Power off disable outputs permit live insertion controls the latch function. When xLEAB is low, the latches are transparent. Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, A subsequent low-to-high transition of xLEAB signal puts the A latches in TA = 25C the storage mode. xOEAB performs output enable function on the B port. Available in SSOP and TSSOP packages Data flow from the B port to the A port is similar but requires using xCEBA, xLEBA, and xOEBA inputs. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16543T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allowlive insertio of boards when used as backplane drivers. FUNCTIONAL BLOCK DIAGRAM 56 29 2OEBA 1OEBA 31 54 2CEBA 1CEBA 55 30 1LEBA 2LEBA 1 28 1OEAB 2OEAB 26 3 2CEAB 1CEAB 27 2 1LEAB 2LEAB C C 15 5 2A1 1A1 52 42 2B1 1B1 D D C C D D TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JULY 2017 1 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5444/6IDT74FCT16543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION PIN DESCRIPTION Pin Names Description 1 56 xOEAB A-to-B Output Enable Input (Active LOW) 1OEAB 1OEBA xOEBA B-to-A Output Enable Input (Active LOW) 2 55 1LEAB 1LEBA xCEAB A-to-B Enable Input (Active LOW) 3 54 xCEBA B-to-A Enable Input (Active LOW) 1CEAB 1CEBA xLEAB A-to-B Latch Enable Input (Active LOW) GND 4 53 GND xLEBA B-to-A Latch Enable Input (Active LOW) 5 52 1A1 1B1 x A x A-to-B Data Inputs or B-to-A 3-State Outputs x B x B-to-A Data Inputs or A-to-B 3-State Outputs 6 51 1A2 1B2 VCC 7 50 VCC (1) 8 49 1A3 1B3 ABSOLUTE MAXIMUM RATINGS 9 48 Symbol Description Max Unit 1A4 1B4 (2) VTERM Terminal Voltage with Respect to GND 0.5 to 7 V 10 47 1A5 1B5 (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V GND 11 46 GND TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 60 to +120 mA 12 45 1A6 1B6 NOTES: 13 44 1A7 1B7 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation 14 43 1A8 1B8 of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating 15 42 2A1 2B1 conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 16 41 2A2 2B2 3. Outputs and I/O terminals for FCT162XXX. 17 40 2A3 2B3 GND 18 39 GND CAPACITANCE (TA = +25C, f = 1.0MHz) 19 38 2A4 2B4 (1) Symbol Parameter Conditions Typ. Max. Unit 20 37 2A5 2B5 CIN Input Capacitance VIN = 0V 3.5 6 pF 21 36 COUT Output Capacitance VOUT = 0V 3.5 8 pF 2A6 2B6 NOTE: VCC 22 35 VCC 1. This parameter is measured at characterization but not tested. 23 34 2A7 2B7 24 33 2A8 2B8 (1, 2) FUNCTION TABLE GND 25 32 GND For A-to-B (Symmetric with B-to-A) Latch Output 26 31 2CEAB 2CEBA Inputs Status Buffers xCEAB xLEAB xOEAB xAx to xBx xBx 27 30 2LEAB 2LEBA H X X Storing Z 28 29 2OEAB 2OEBA X H X Storing X L L L Transparent Current A Inputs TOP VIEW L H L Storing Previous* A Inputs L L H Transparent Z Package Type Package Code Order Code L H H Storing Z NOTES: TSSOP PAG56 PAG 1. * Before xLEAB LOW-to-HIGH Transition SSOP PVG56 PVG H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care 2. A-to-B data flow shown B-to-A flow control is the same, except using xCEBA, xLEBA and xOEBA. 2