74FCT16952CTPVG8 Renesas

IDT74FCT16952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE FAST CMOS IDT74FCT16952AT/CT/ET 16-BIT REGISTERED TRANSCEIVER FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT16952T 16-bit registered transceiver is built using advanced High-speed, low-power CMOS replacement for ABT functions dual metal CMOS technology. These high-speed, low-power devices are Typical tSK(o) (Output Skew) < 250ps organized as two independent 8-bit D-type registered transceivers with Low input and output leakage 1A (max.) separate input and output control for independent control of data flow in either High drive outputs (-32mA IOH, 64mA IOL) direction. For example, the A-to-B Enable (xCEAB) must be low to enter Power off disable outputs permit live insertion data from the A port. xCLKAB controls the clocking function. When xCLKAB Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, toggles from low-to-high, the data present on the A port will be clocked into TA = 25C the register. xOEAB performs the output enable function on the B port. Data Available in SSOP and TSSOP packages flow from the B port to A port is similar but requires using xCEBA, xCLKBA, and xOEBA inputs. Full 16-bit operation is achieved by tying the control pins of the independent transceivers together. The FCT16952T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability allowinglive insertio of boards when used as backplane drivers. FUNCTIONAL BLOCK DIAGRAM 54 31 1CEBA 2CEBA 55 30 1CLKBA 2CLKBA 28 1 2OEAB 1OEAB 3 26 2CEAB 1CEAB 2 27 2CLKAB 1CLKAB 29 56 1OEBA 2OEBA C C 5 15 CE CE 2A1 1A1 52 42 D D 1B1 2B1 C C CE CE D D TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE MAY 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5442/7IDT74FCT16952AT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION PIN DESCRIPTION Pin Names Description xOEAB A-to-B Output Enable Input (Active LOW) 1 56 1OEAB 1OEBA xOEBA B-to-A Output Enable Input (Active LOW) 2 55 1CLKAB 1CLKBA xCEAB A-to-B Clock Enable Input (Active LOW) 3 54 1CEAB 1CEBA xCEBA B-to-A Clock Enable Input (Active LOW) GND 4 53 GND xCLKAB A-to-B Clock Input 5 52 1A1 1B1 xCLKBA B-to-A Clock Input 6 51 x A x A-to-B Data Inputs or B-to-A 3-State Outputs 1A2 1B2 x B x B-to-A Data Inputs or A-to-B 3-State Outputs VCC 7 50 VCC 8 49 1A3 1B3 9 48 (1) 1A4 1B4 ABSOLUTE MAXIMUM RATINGS 10 47 1A5 1B5 Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V GND 11 46 GND (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 12 45 1A6 1B6 TSTG Storage Temperature 65 to +150 C 13 44 1A7 1B7 IOUT DC Output Current 60 to +120 mA 14 43 1A8 1B8 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 15 42 2A1 2B1 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational 16 41 2A2 2B2 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 17 40 2A3 2B3 2. All device terminals except FCT162XXX Output and I/O terminals. GND 18 39 GND 3. Output and I/O terminals for FCT162XXX. 19 38 2A4 2B4 20 37 2A5 2B5 CAPACITANCE (TA = +25C, F = 1.0MHz) 21 36 2A6 2B6 (1) Symbol Parameter Conditions Typ. Max. Unit VCC 22 35 VCC CIN Input Capacitance VIN = 0V 3.5 6 pF 23 34 COUT Output Capacitance VOUT = 0V 3.5 8 pF 2A7 2B7 24 33 NOTE: 2A8 2B8 1. This parameter is measured at characterization but not tested. GND 25 32 GND (1,3) 26 31 FUNCTION TABLE 2CEAB 2CEBA Inputs Outputs 27 30 2CLKAB 2CLKBA xCEAB xCLKAB xOEAB xAx xBx 28 29 2OEAB 2OEBA (2) HX L X B (2) XL L X B L LL L TOP VIEW L LH H Package Type Package Code Order Code XX H X Z TSSOP PAG56 PAG NOTES: SSOP PVG56 PVG 1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA, and xOEBA. 2. Level of B before the indicated steady-state input conditions were established. 3. H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care = LOW-to-HIGH Transition Z = High-impedance 2