74FCT2373ATQG Renesas

IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE FAST CMOS OCTAL IDT74FCT2373AT/CT TRANSPARENT LATCH DESCRIPTION: FEATURES: The FCT2373T is an octal transparent latch built using an advanced dual A and C grades metal CMOS technology. These octal latches have 3-state outputs and are Low input and output leakage 1A (max.) intended for bus oriented applications. The flip-flops appear transparent to CMOS power levels the data when Latch Enable (LE) is high. When LE is low, the data that meets True TTL input and output compatibility: the set-up time is latched. Data appears on the bus when the Output Enable VOH = 3.3V (typ.) (OE) is low. When OE is high, the bus output is in the high-impedance state. VOL = 0.3V (typ.) The FCT2373T has balanced drive outputs with current limiting resis- Meets or exceeds JEDEC standard 18 specifications tors. This offers low ground bounce, minimal undershoot and controlled Resistor outputs -15mA IOH, 12mA IOL output fall times-reducing the need for external series terminating resistors. Reduced system switching noise The FCT2373T parts are plug-in replacements for FCT373T parts. Available in QSOP package FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 D D D D D D D D O O O O O O O O G G G G G G G G LE OE O0 O1 O2 O3 O4 O5 O6 O7 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2009 1 2009 Integrated Device Technology, Inc. DSC-5497/7IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 20 VCC OE 1 TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 60 to +120 mA 19 O0 2 O7 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause D0 18 3 D7 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating D1 4 17 D6 conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. O1 16 O6 5 3. Output and I/O terminals only. O5 O2 6 15 CAPACITANCE (TA = +25C, F = 1.0MHz) D2 D5 14 7 (1) Symbol Parameter Conditions Typ. Max. Unit D3 D4 8 13 CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF O3 9 12 O4 NOTE: 1. This parameter is measured at characterization but not tested. LE 11 GND 10 QSOP TOP VIEW PIN DESCRIPTION Pin Names Description Dx Data Inputs LE Latch Enable Input (Active HIGH) OE Output Enable Input (Active LOW) O x 3-State Outputs (1) FUNCTION TABLE Inputs Outputs Dx LE OE Ox LH L L HH L H XX H Z NOTE: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High Impedance 2