74FCT3245AQG8 Renesas

IDT74FCT3245/A 3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS OCTAL IDT74FCT3245/A BIDIRECTIONAL TRANSCEIVER FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT3245/A octal transceivers are built using advanced dual metal ESD > 2000V per MIL-STD-883, Method 3015 > 200V using CMOS technology. These high-speed, low-power transceivers are ideal machine model (C = 200pF, R = 0) for asynchronous communication between two buses (A and B). The VCC = 3.3V 0.3V, Normal Range direction control pin (DIR) controls the direction of data flow. The output VCC = 2.7V to 3.6V, Extended Range enable pin (OE) overrides the direction control and disables both ports. All CMOS power levels (0.4W typ. static) inputs are designed with hysteresis for improved noise margin. Rail-to-Rail output swing for increased noise margin The FCT3245/A has series current limiting resistors. These offer low Available in QSOP and TSSOP packages ground bounce, minimal undershoot, and controlled output fall times- reducing the need for external series terminating resistors. FUNCTIONAL BLOCK DIAGRAM 1 DIR 19 OE 2 A1 18 B1 3 A2 17 B2 4 A3 16 B3 5 A4 15 B4 6 A5 14 B5 7 A6 13 B6 8 A7 12 B7 9 A8 11 B8 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE MAY 2018 1 2018 Integrated Device Technology, Inc. DSC-2650/16IDT74FCT3245/A 3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE (1) ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V (3) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V DIR Vcc 1 20 (4) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V A1 OE 2 19 TSTG Storage Temperature 65 to +150 C A 2 IOUT DC Output Current 60 to +60 mA B 1 3 18 NOTES: A3 2 B 4 17 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may A4 3 B cause permanent damage to the device. This is a stress rating only and functional 5 16 operation of the device at these or any other conditions above those indicated in 5 A B4 the operational sections of this specification is not implied. Exposure to absolute 6 15 maximum rating conditions for extended periods may affect reliability. A6 5 B 7 14 2. VCC terminals. 7 A B6 3. Input terminals. 8 13 4. Outputs and I/O terminals. A8 B7 9 12 GND 8 B 10 11 QSOP/ TSSOP CAPACITANCE (TA = +25C, F = 1.0MHz) TOP VIEW (1) Symbol Parameter Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 3.5 6 pF COUT Output Capacitance VOUT = 0V 4 8 pF NOTE: 1. This parameter is measured at characterization but not tested. PIN DESCRIPTION Pin Names Description OE 3State Output Enable Inputs (Active LOW) DIR Direction Control Output A x Side A Inputs or 3-State Outputs B x Side B Inputs or 3-State Outputs (1) FUNCTION TABLE Inputs OE DIR Outputs L L Bus B Data to Bus A L H Bus A Data to Bus B H X High Z State NOTE: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High Impedance 2