74FCT521ATSOG Renesas

74FCT521AT/CT FAST CMOS 8-BIT IDENTITY COMPARATOR INDUSTRIAL TEMPERATURE RANGE FAST CMOS 8-BIT 74FCT521AT/CT IDENTITY COMPARATOR FEATURES: DESCRIPTION: A and C grades The IDT74FCT521T is an 8-bit identity comparator built using an Low input and output leakage 1A (max.) advanced dual metal CMOS technology. These devices compare two CMOS power levels words of up to eight bits each and provide a low output when the two words True TTL input and output compatibility: match bit for bit. The expansion input IA = B also serves as an active low VOH = 3.3V (typ.) enable input. VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Power off disable outputs permitlive insertio Available in SOIC and QSOP packages FUNCTIONAL BLOCK DIAGRAM 2 A0 3 B0 4 A1 5 B1 6 A2 7 B2 8 A3 9 B3 19 OA=B 11 A4 12 B4 13 A5 14 B5 15 A6 16 B6 17 A7 18 B7 1 IA=B INDUSTRIAL TEMPERATURE RANGE 1 Feb.11.2074FCT521AT/CT FAST CMOS 8-BIT IDENTITY COMPARATOR INDUSTRIAL TEMPERATURE RANGE (1) ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 20 IA=B 1 VCC TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 60 to +120 mA 19 2 OA=B A0 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause B0 18 3 B7 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating A1 4 17 A7 conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. B1 16 B6 5 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. A6 A2 6 15 B2 B5 7 14 CAPACITANCE (TA = +25C, F = 1.0MHz) A5 (1) A3 13 8 Symbol Parameter Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF 12 B4 9 B3 COUT Output Capacitance VOUT = 0V 8 12 pF A4 11 NOTE: GND 10 1. This parameter is measured at characterization but not tested. TOP VIEW Package Type Package Code Order Code QSOP PCG20 QG PIN DESCRIPTION SOIC PSG20 SOG Pin Names Description A0 - A7 Word A Inputs B0 - B7 Word B Inputs IA = B Expansion or Enable Input (Active LOW) OA = B Identity Output (Active LOW) (1) FUNCTION TABLE Inputs Output IA = B A, B OA = B L A = B* L LA BH H A = B* H HA BH NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level *A0 = B0, A1 = B1, A2 = B2, etc. 2 Feb.11.20