74FCT540ATQG Renesas

74FCT540AT/CT FAST CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE FAST CMOS OCTAL 74FCT540AT/CT BUFFER/LINE DRIVER FEATURES: DESCRIPTION: A and C grades The IDT octal buffer/line driver is built using an advanced dual metal Low input and output leakage 1A (max.) CMOS technology. The FCT540T is similar in function to the FCT240T, CMOS power levels except that the inputs and outputs are on opposite sides of the package. This True TTL input and output compatibility: pinout arrangement makes these devices especially useful as output ports VOH = 3.3V (typ.) for microprocessors and as backplane drivers, allowing ease of layout and VOL = 0.3V (typ.) greater board density. High Drive outputs (-15mA IOH, 64mA IOL) Meets or exceeds JEDEC standard 18 specifications Power off disable outputs permitlive insertio Available in SOIC and QSOP packages FUNCTIONAL BLOCK DIAGRAM OEA OEB D0 O0 D1 O1 D2 O2 D3 O3 D4 O4 D5 O5 D6 O6 D7 O7 INDUSTRIAL TEMPERATURE RANGE 1 Feb.11.2074FCT540AT/CT FAST CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE (1) ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 20 1 OEA VCC TSTG Storage Temperature 65 to +150 C 19 D0 2 OEB IOUT DC Output Current 60 to +120 mA 18 3 O0 NOTES: D1 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause 17 4 D2 O1 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational 16 D3 5 O2 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed 15 D4 6 O3 Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 14 D5 7 O4 3. Output and I/O terminals only. 13 D6 8 O5 12 9 D7 O6 11 GND 10 CAPACITANCE (TA = +25C, F = 1.0MHz) O7 (1) Symbol Parameter Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF TOP VIEW COUT Output Capacitance VOUT = 0V 8 12 pF Package Type Package Code Order Code NOTE: 1. This parameter is measured at characterization but not tested. QSOP PCG20 QG SOIC PSG20 SOG PIN DESCRIPTION Pin Names Description OEA, OEB 3-State Output Enable Inputs (Active LOW) Dx Inputs O x Outputs (1) FUNCTION TABLE Inputs OEA OEB D Outputs LLL H LL H L HH X Z NOTE: 1. H = HIGH Voltage Level X = Dont Care L = LOW Voltage Level Z = High Impedance 2 Feb.11.20