74FCT543ATSOG8 Renesas

74FCT543AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE FAST CMOS 74FCT543AT/CT OCTAL LATCHED TRANSCEIVER FEATURES: DESCRIPTION: A and C grades The FCT543T is a non-inverting octal transceiver built using an advanced Low input and output leakage 1A (max.) dual metal CMOS technology. This device contains two sets of eight D-type CMOS power levels latches with separate input and output controls for each set. For data flow True TTL input and output compatibility: from A to B, for example, the A-to-B Enable (CEAB) input must be low in order VOH = 3.3V (typ.) to enter data from A0A7 or to take data from B0B7, as indicated in the VOL = 0.3V (typ.) Function Table. With CEAB low, a low signal on the A-to-B Latch Enable High Drive outputs (-15mA IOH, 64mA IOL) (LEAB) input makes the A-to-B latches transparent a subsequent low-to- Meets or exceeds JEDEC standard 18 specifications high transition of the LEAB signal puts the A latches in the storage mode and Power off disable outputs permitlive insertio their outputs no longer change with the A inputs. With CEAB and OEAB both Available in SOIC and QSOP packages low, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses the CEBA, LEBA and OEBA inputs. FUNCTIONAL BLOCK DIAGRAM DETAIL A D Q 0 B LE A0 Q D LE 1 1 A B A2 B2 A3 B3 A4 DETAIL A x 7 B4 5 5 A B A6 B6 A7 B7 OEBA OEAB CEBA LEBA CEAB LEAB INDUSTRIAL TEMPERATURE RANGE 1 Feb.11.2074FCT543AT/CT FAST CMOS OCTAL LATCHED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V (3) LEBA 1 24 VCC VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V TSTG Storage Temperature 65 to +150 C 23 OEBA 2 CEBA IOUT DC Output Current 60 to +120 mA A0 22 NOTES: 3 B0 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation A1 4 21 B1 of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating A2 5 20 B2 conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. B3 A3 19 6 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. B4 A4 18 7 A5 B5 8 17 CAPACITANCE (TA = +25C, F = 1.0MHz) 9 16 B6 A6 (1) Symbol Parameter Conditions Typ. Max. Unit B7 A7 10 15 CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF 14 LEAB 11 CEAB NOTE: 1. This parameter is measured at characterization but not tested. OEAB 13 GND 12 TOP VIEW Package Type Package Code Order Code PIN DESCRIPTION QSOP PCG24 QG Pin Names Description SOIC PSG24 SOG OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) CEBA B-to-A Enable Input (Active LOW) LEAB A-to-B Latch Enable Input (Active LOW) LEBA B-to-A Latch Enable Input (Active LOW) A0A7 A-to-B Data Inputs or B-to-A 3-State Outputs B0B7 B-to-A Data Inputs or A-to-B 3-State Outputs 2 Feb.11.20