18-Port, 48-Lane, 240Gbps, CPS-1848 Datasheet Gen2 RapidIO Switch Description Features RapidIO ports The CPS-1848 (80HCPS1848) is a RapidIO Specification (Rev. 2.1) compliant Secure Packet Switch whose functionality is central to 48 bidirectional S-RIO lanes routing packets for distribution among DSPs, processors, FPGAs, Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port other switches, or any other RapidIO-based devices. It can also be Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud used in RapidIO backplane switching. The CPS-1848 supports Serial Support Level I defined short or long haul reach, and Level II RapidIO (S-RIO) packet switching (unicast, multicast, and an optional defined short-, medium-, or long-run reach for each PHY speed broadcast) from any of its 18 input ports to any of its 18 output ports. Error Management Extensions support Software-assisted error recovery, supporting hot swap Block Diagram 2 I C Interfaces 2 Provides I C port for maintenance and error reporting Quadrant 0 Quadrant 3 Master or Slave operation Lanes 0-3, 16-19, 32-35 Lanes 12-15, 28-31, 44-47 Master allows power-on configuration from external ROM Ports 0, 4, 8, 12, 16 Ports 3, 7, 11, 15 Master mode configuration with external image compressing and checksum Switch CPS-1848 RapidIO Gen2 240 Gbps peak throughput Switch Fabric Non-blocking data flow architecture Configurable for Cut-Through or Store-and-Forward data flow Event Management and Maintenance Very low latency for all packet lengths and load conditions Registers Internal queuing buffer and retransmit buffer 2 I C Controller JTAG Controller Standard transmitter- or receiver-controlled flow control Global routing or Local Port routing capability Ports 1, 5, 9, 13, 17 Ports 2, 6, 10, 14 Supports up to 40 simultaneous multicast masks, with broadcast Lanes 4-7, 20-23, 36-39 Lanes 8-11, 24-27, 40-43 Performance monitoring counters for performance and Quadrant 1 Quadrant 2 diagnostics analysis. Per input port and output port counters SerDes Transmitter pre-emphasis and drive strength + receiver Typical Applications equalization provides best possible signal integrity Embedded PRBS generation and detection with programmable High-performance computing polynomials support Bit Error Rate testing Wireless Additional Information Defense and aerospace Packet Trace/Mirror. Each input port can copy all incoming Video and imaging packets matching user-defined criteria to a trace output port. Packet Filter. Each input port can filter (drop) all incoming packets matching user-defined criteria. 2 Device configurable through any of S-RIO ports, I C, or JTAG Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6) Lidless 784-FCBGA Package: 29 29 mm, 1.0 mm ball pitch 2019 Integrated Device Technology, Inc. 1 March 15, 2019CPS-1848 Datasheet Table of Contents 1. About This Document ........................................................................................................................................................................................ 4 Introduction............................................................................................................................................................................................................ 4 Additional Resources............................................................................................................................................................................................. 4 Document Conventions and Definitions................................................................................................................................................................. 4 Revision History..................................................................................................................................................................................................... 4 2. Device Description ............................................................................................................................................................................................. 6 Specification Compliancy....................................................................................................................................................................................... 7 3. Functional Overview........................................................................................................................................................................................... 7 4. Interface Overview.............................................................................................................................................................................................. 8 S-RIO Ports ........................................................................................................................................................................................................... 8 I2C Bus.................................................................................................................................................................................................................. 8 JTAG TAP Port...................................................................................................................................................................................................... 8 Interrupt (IRQ N)................................................................................................................................................................................................... 8 Reset (RST N) ...................................................................................................................................................................................................... 8 Clock (REF CLK P/N) .......................................................................................................................................................................................... 8 Rext (REXT N/P) .................................................................................................................................................................................................. 9 Speed Select (SPD 2:0 )........................................................................................................................................................................................ 9 Quadrant Config (QCFG 7:0 )................................................................................................................................................................................ 9 Frequency Select (FSEL 1:0 ) ............................................................................................................................................................................... 9 Multicast (MCAST)................................................................................................................................................................................................. 9 5. Configuration Pins............................................................................................................................................................................................ 10 Speed Select Pins SPD 2:0 ................................................................................................................................................................................ 10 Quadrant Configuration Pins QCFG 7:0 ............................................................................................................................................................. 10 6. Absolute Maximum Ratings............................................................................................................................................................................. 14 7. Recommended Operating Conditions ............................................................................................................................................................ 15 8. AC Test Conditions .......................................................................................................................................................................................... 16 9. Power Consumption......................................................................................................................................................................................... 18 2 10. I C Bus............................................................................................................................................................................................................... 19 2 I C Master Mode and Slave Mode....................................................................................................................................................................... 19 2 I C Device Address ............................................................................................................................................................................................. 19 Signaling.............................................................................................................................................................................................................. 20 Read/Write Figures.............................................................................................................................................................................................. 21 2 I C DC Electrical Specifications........................................................................................................................................................................... 23 2 I C AC Electrical Specifications........................................................................................................................................................................... 24 2 I C Timing Waveforms......................................................................................................................................................................................... 25 11. Interrupt (IRQ N) Electrical Specifications .................................................................................................................................................... 26 12. Configuration (Static) Pin Specification......................................................................................................................................................... 27 13. S-RIO Ports........................................................................................................................................................................................................ 28 Overview.............................................................................................................................................................................................................. 28 Definition of Amplitude and Swing....................................................................................................................................................................... 29 1.25, 2.5, and 3.125 Gbaud LP-Serial Links........................................................................................................................................................ 30 Level I Electrical Specification ............................................................................................................................................................................. 30 5 and 6.25 Gbaud LP-Serial Links....................................................................................................................................................................... 37 Level II Electrical Specifications .......................................................................................................................................................................... 37 2019 Integrated Device Technology, Inc. 2 March 15, 2019