8-Port Serial Datasheet RapidIO Switch 80KSW0003 u Performance 1 Device Overview 20 Gbps of peak switching bandwidth The CPS-8, device number IDT80KSW0003, is a serial RapidIO (sRIO) switch Non-blocking data flow architecture within each sRIO priority Very low latency for all packet length and load condition whose functionality is central to routing packets for distribution among DSPs, Internal queuing buffer and retransmit buffer processors, FPGAs, other switches, or any other sRIO-based devices. It may Standard receiver based physical layer flow control also be used in serial RapidIO backplane switching. The CPS-8 supports serial u Features RapidIO packet switching (unicast, multicast, and an optional broadcast) from Configurable for Cut Through or Store And Forward data flow any of its 8 input ports to any of its 8 output ports. 2 Device configurable through any of sRIO ports, I C, or JTAG Packet Trace. Each port provides the ability to match the first 160 bits of any packet against up to 4 programmable comparison values to 2 Features copy the packet to a programmable output trace port u Packet Filter. Each port also provides the ability to filter the packet Interfaces - sRIO based on comparisons against these same 4 programmable values 8 bidirectional serial RapidIO (sRIO) lanes v 1.3 mentioned above Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps Supports up to 10 simultaneous multicast masks All lanes support short haul or long haul reach for each PHY speed Broadcast support Configurable port count to up to eight 1x ports, two 4x ports, or 4 1x Port Loopback Debug Feature and 1 4x ports Software assisted error recovery, supporting hot swap Lanes can be configured as individual non-redundant 1x ports, as part Ports may be individually turned off to reduce power of a redundant 1x port, or as part of a 4x port PMON counters for monitor and diagnostics. Per input port and Support for two separate port rates for each quad output port counters Supports standard 4 levels of priority SerDes physical diagnostic registers Error management support Embedded PRBS generation and detection with programmable poly- u 2 Interfaces - I C nomials support Bit Error Rate (BER) testing 2 Provides I C port for maintenance and error reporting 0.13um technology Master or Slave Operation Low power dissipation Master allows power-on configuration from external ROM Full JTAG Boundary Scan Support (IEEE1149.1 & 1149.6) Master mode configuration with external image compressing and Package: 324-ball grid array, 19mm x 19mm, 1.0mm ball pitch checksum 3 Block Diagram S erial R a pidIO S w itch Ln0 Ln4 sR IO sR IO Ln1 Ln5 E n ha n c ed E n ha n c ed Ln2 Ln6 Q uad Qu a d Ln3 ( up t o 4 por t s ) ( up t o 4 por t s ) Ln7 M ainten anc e & Erro r M a nag em en t 2 JT A G C onfiguratio n I C Figure 1 Block diagram 1 of 47 March 31, 2008 DSC 5697IDT80KSW0003 Datasheet 4 Device Description The CPS-8 is optimized for DSP cluster applications at board level. Its main function is to have a backplane interface which can connect to a back- plane switch or directly to multiple RF cards. On the line card side it can also connect to multiple ports. It supports up to 8 ports which are configurable as line card, or backplane ports. It is an end-point free (switch) device in an sRIO network. The CPS-8 receives packets from up to 8 ports. The CPS offers full support for normal switching as well as enhanced functions: 1) Normal Switching: All packets are switched in accordance with standard serial RapidIO specifications, with packet destination IDs determining how the packet is routed. Three major options exist within this category: a. Multicast: If a Multicast ID is received, the CPS-8 performs a multicast as defined in the sRIO multicast registers. b. Unicast: All other operations are performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. The sRIO Switch supports a peak throughput of 20 Gbps which is the line rate for 8 ports in 1x configuration, each at 2.5 Gbps (3.125 Gbps minus the sRIO-defined 8b10b encoding), and switches dynamically in accordance with the packet headers and priorities. 2) Enhanced functions Enhanced features are provided for support of system debug. These features which are optional for the user consist of two major functions: a. Packet Trace: The Packet Trace feature provides at-speed checking of the first 160 bits (header plus a portion of any payload) of every incom- ing packet against user-defined comparison register values. The trace feature is available on all serial RapidIO ports, each acting indepen- dently from one another. If the trace feature is enabled for a given port, every incoming packet is checked for a match against up to four comparison registers. In the event of a match, either of two possible user defined actions may take place: i) not only does the packet route normally through the switch to its appropriate destination port, but this same packet is replicated and sent to a trace port. The trace port itself may be any of the standard serial RapidIO ports. The port used for the trace port is defined by the user through simple register configuration. ii) the packet is dropped. If there is no match, the packets route normally through the switch with no action taken. The Packet Trace feature can be used during system bring-up and prototyping to identify particular packet types of interest to the user. It might be used in security applications, where packets must be checked for either correct or incorrect tags in either of the header or payload. Identi- fied (match) packets are then routed to the trace port for receipt by a host processor, which can perform an intervention at the software level. b. Port Loopback: The CPS-8 offers internal loopback for each port that may be used for system debug of the high speed sRIO ports. By enabling loopback on a given port, packets sent to the ports receiver are immediately looped back at the physical layer to the transmitter - bypassing the higher logical or transport layers. c. Broadcast: Each multicast mask can be configured so that the source port is included among the destination ports for that multicast operation. 2 The CPS-8 can be programmed through any one or combination of sRIO, I C, or JTAG. Note that any sRIO port may be used for programming. The 2 CPS-8 can also configure itself on power-up by reading directly from ROM over I C in master mode. 2 of 47 March 31, 2008