Dual VCXO w/3.3V, 2.5V LVPECL 813001I FemtoClock PLL DATASHEET GENERAL DESCRIPTION FEATURES The 813001I is a dual VCXO + FemtoClock Multiplier de- One 3.3V or 2.5V LVPECL output pair signed for use in Discrete PLL loops. Two selectable external Two selectable crystal oscillator interfaces for the VCXO, VCXO crystals allow the device to be used in multi-rate appli- one differential clock or one LVCMOS/LVTTL clock inputs cations, where a given line card can be switched, for example, CLK1/nCLK1 supports the following input types: between 1Gb Ethernet (125MHz system reference clock) and LVPECL, LVDS, LVHSTL, SSTL, HCSL 1Gb Fibre Channel (106.25MHz system reference clock) modes. Of course, a multitude of other applications are also possible Crystal operating frequency range: 14MHz - 24MHz such as switching between 74.25MHz and 74.175824MHz for VCO range: 490MHz - 640MHz HDTV, switching between SONET, FEC and non FEC rates, etc. Output frequency range: 40.83MHz - 640MHz The 813001I is a two stage device a VCXO followed VCXO pull range: 100ppm (typical) by a FemtoClock PLL. The FemtoClock PLL can multiply Supports the following applications (among others): the crystal frequency of the VCXO to provide an output SONET, Ethernet, Fibre Channel, HDTV, MPEG frequency range of 40.83MHz to 640MHz, with a random rms phase jitter of less than 1ps (12kHz 20MHz). This phase jitter RMS phase jitter 622.08MHz (12kHz - 20MHz): performance meets the requirements of 1Gb/10Gb Ethernet, 0.84 (typical) 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to Supply voltage modes: OC48. The FemtoClock PLL can also be bypassed if frequen- V /V CC CCO cy multiplication is not required. For testing/debug purposes, 3.3V/3.3V de-assertion of the output enable pin will place both Q and nQ 3.3V/2.5V in a high impedance state. 2.5V/2.5V -40C to 85C ambient operating temperature Available in RoHS/Lead-Free compliant package BLOCK DIAGRAM Pullup VCO SEL Pulldown CLK SEL0 Pullup CLK SEL1 Pulldown CLK0 0 0 Pulldown 0 CLK1 Output Divider N Pullup 0 1 nCLK1 N2:N0 000 1 XTAL IN0 VCO 001 2 PD 1 490-640MHz 010 3 Q 1 0 011 4 (default) XTAL OUT0 nQ (default) 100 5 Feedback Divider M 101 6 VCXO PIN ASSIGNMENT XTAL IN1 110 8 M2:M0 CLK SEL1 111 12 VCO SEL 1 24 000 16 N0 2 23 CLK SEL0 1 1 001 20 XTAL OUT1 OE N1 3 22 010 22 N2 4 M2 011 24 21 100 25 (default) VCCO 5 20 M1 6 101 32 19 M0 Q 110 40 7 nQ 18 CLK1 VC 111 MR 8 nCLK1 VEE 17 Pullup 9 CLK0 M2 VCCA 16 Pulldown VCC 10 VC 15 M1 XTAL IN0 XTAL OUT1 11 14 Pulldown M0 12 13 XTAL OUT0 XTAL IN1 Pulldown N2 813001I Pullup N1 24-Lead TSSOP Pullup N0 4.40mm x 7.8mm x 0.92mm Pullup package body OE G Package Top View 813001I REVISION A 3/17/15 1 2015 Integrated Device Technology, Inc.813001I DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VCO SEL Input Pullup VCO select pin. LVCMOS/LVTTL interface levels. 2, 3 N0, N1 Input Pullup Output divider select pins. Default value = 4. LVCMOS/LVTTL interface levels. 4 N2 Input Pulldown 5V Power Output supply pin. CCO 6, 7 Q, nQ Ouput Differential output pair. LVPECL interface levels. 8V Power Negative supply pin. EE 9V Power Analog supply pin. CCA 10 V Power Core supply pin. CC 11 XTAL OUT1, Parallel resonant crystal interface. XTAL OUT1 is the output, Input 12 XTAL IN1 XTAL IN1 is the input. 13 XTAL OUT0, Parallel resonant crystal interface. XTAL OUT0 is the output, Input 14 XTAL IN0 XTAL IN0 is the input. 15 VC Input VCXO control voltage input. 16 CLK0 Input Pulldown LVCMOS/LVTTL clock input. 17 nCLK1 Input Pullup Inverting differential clock input. 18 CLK1 Input Pulldown Non-inverting differential clock input. 19, 20 M0, M1 Input Pulldown Feedback divider select pins. Default value = 25. LVCMOS/LVTTL interface levels. 21 M2 Input Pullup Output enable. When HIGH, the output is active. When LOW, the output is 22 OE Input Pullup in a high impedance state. LVCMOS/LVTTL interface levels. 23 CLK SEL0 Input Pulldown Clock select pin. LVCMOS/LVTTL interface levels. Refer to Table 3. 24 CLK SEL1 Input Pullup NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP TABLE 3. CONTROL INPUT FUNCTION TABLE Inputs CLK SEL1 CLK SEL0 Selected Input 0 0 CLK0 0 1 CLK1, nCLK1 1 0 XTAL0 1 1 XTAL1 DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK PLL 2 REVISION A 3/17/15