FemtoClock Dual VCXO Video PLL 810001-21 Data Sheet General Description Features The 810001-21 is a PLL based synchronous clock generator that is Jitter attenuation and frequency translation of video clock signals optimized for digital video clock jitter attenuation and frequency Supports SMPTE 292M, ITU-R Rec. 601/656 and translation. The device contains two internal frequency multiplication MPEG-transport clocks stages that are cascaded in series. The first stage is a VCXO PLL Support of High-Definition (HD) and Standard-Definition (SD) that is optimized to provide reference clock jitter attenuation, and to pixel rates support the complex PLL multiplication ratios needed for video rate Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates conversion. The second stage is a FemtoClock frequency in one device multiplier that provides the low jitter, high frequency video output Supports both 1000/1001 and 1001/1000 rate conversions clock. Dual PLL mode for high-frequency clock generation (36MHz to Preset multiplication ratios are selected from internal lookup tables 148.5MHz) using device input selection pins. The multiplication ratios are VCXO-PLL mode for low-frequency clock generation (27MHz and optimized to support most common video rates used in professional 26.973MHz) video system applications. The VCXO requires the use of an One LVCMOS/LVTTL clock output external, inexpensive pullable crystal. Two crystal connections are Two selectable LVCMOS/LVTTL clock inputs provided (pin selectable) so that both 60 and 59.94 base frame rates can be supported. The VCXO requires external passive loop filter LVCMOS/LVTTL compatible control signals components which are used to set the PLL loop bandwidth and RMS phase jitter 148.3516MHz, (12kHz - 20MHz): damping characteristics. 1.089ps (typical) 3.3V supply voltage 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) packages Supported Input Frequencies Supported Output Frequencies f = 27MHz f = 26.973MHz f = 27MHz f = 26.973MHz VCXO VCXO VCXO VCXO 27.0000MHz 26.9730MHz 148.5000MHz 148.3515MHz 27.0270MHz 27.0000MHz 74.2500MHz 74.1758MHz 74.1758MHz 74.1016MHz 49.5000MHz 49.4505MHz 74.3243MHz 74.2499MHz 33.0000MHz 32.9670MHz 74.2500MHz 74.1758MHz 162.0000MHz 161.8380MHz 27.0270MHz 27.0000MHz 81.0000MHz 80.9190MHz 26.9730MHz 26.9461MHz 54.0000MHz 53.9460MHz 74.1758MHz 74.1016kHz 36.0000MHz 35.9640MHz 45.0000kHz 44.9550kHz 27.0000MHz 26.9730MHz 33.7500kHz 33.7163kHz 15.6250kHz 15.6094kHz 15.7343kHz 15.7185kHz 28.1250kHz 28.0969kHz 2016 Integrated Device Technology, Inc 1 Revision B March 3, 2016810001-21 Data Sheet Block Diagram Loop Filter 01 Phase VCXO Input Pulldown Detector CLK0 0 Pre-Divider VCXO Pulldown (P Value CLK1 1 Charge from Table) Pump Pulldown CLK SEL VCXO Feedback Divider (M Value from Table) VCXO Pulldown 4 V3:V0 Divider VCXO Jitter Attenuation PLL Table 00 01 Output FemtoClock Divider Q 01 10 Frequency Multiplier 10 10 Pullup 00 = 4 (default) 11 OE 11 0= x22 (default) 11 01 = 8 1= x24 10 = 12 Pulldown MR Master Reset 11 = 18 Pulldown MF 2 Pulldown N1:N0 2 Pullup nBP1:nBP0 Pin Assignment 32 31 30 29 28 27 26 25 LF1 1 N0 24 LF0 2 23 N1 810001-21 ISET 3 22 nBP1 32 Lead VFQFN V 4 OE DD 21 5mm x 5mm x 0.925mm nBP0 5 20 GND package body 6 GND 19 Q K Package 7 V CLK SEL 18 DDO Top View CLK1 8 V 17 DDA 9 10 11 12 13 14 15 16 2016 Integrated Device Technology, Inc 2 Revision B March 3, 2016 CLK0 VDDX V0 XTAL IN0 VDD XTAL OUT0 MR GND XTAL IN1 MF V1 XTAL OUT1 V2 XTAL SEL V3 VDD ISET LF0 LF1 XTAL IN0 XTAL OUT0 XTAL IN1 XTAL OUT1 Pulldown XTAL SEL