nCLK1 CLK1 VCC nCLK0 CLK0 XTAL OUT XTAL IN VCCX Jitter Attenuator & FemtoClock ICS813252I-02 Multiplier OBSOLETE DATA SHEET GENERAL DESCRIPTION FEATURES The ICS813252I-02 is a PLL based synchronous multiplier that is Two LVPECL outputs optimized for PDH or SONET to Ethernet clock jitter attenuation Each output supports independent frequency selection at and frequency translation. The device contains two internal 25MHz, 125MHz, 156.25MHz and 312.5MHz frequency multiplication stages that are cascaded in series. The rst Two differential inputs support the following input types: LVPE- stage is a VCXO PLL that is optimized to provide reference clock CL, LVDS, LVHSTL, SSTL, HCSL jitter attenuation. The second stage is a FemtoClock frequency Accepts input frequencies from 8kHz to 155.52MHz including multiplier that provides the low jitter, high frequency Ethernet 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter 125MHz and 155.52MHz requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication Attenuates the phase jitter of the input clock by using a low- ratios are optimized to support most common clock rates used in cost pullable fundamental mode VCXO crystal PDH, SONET and Ethernet applications. The VCXO requires the VCXO PLL bandwidth can be optimized for jitter attenuation use of an external, inexpensive pullable crystal. The VCXO uses and reference tracking using external loop lter connection external passive loop lter components which allows con guration FemtoClock frequency multiplier provides low jitter, high fre- of the PLL loop bandwidth and damping characteristics. The quency output device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. Absolute pull range: 50ppm FemtoClock VCO frequency: 625MHz RMS phase jitter 125MHz, using a 25MHz crystal (10kHz 20MHz): 1.3ps (maximum) 3.3V supply voltage -40C to 85C ambient operating temperature PIN ASSIGNMENT Available in lead-free (RoHS 6) package For functional replacement device use 813N252CKI-02LF 32 31 30 29 28 27 26 25 LF1 1 24 VEE LF0 2 23 nQB ISET 3 22 QB VEE 4 21 VCCO ICS813252I-02 CLK SEL 5 20 nQA 6 VCC 19 QA RESERVED 7 18 VEE VEE 8 17 ODASEL 0 9 10 11 12 13 14 15 16 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View ICS813252CKI-02 REVISION A AUGUST 4, 2016 1 2016 Integrated Device Technology, Inc. PDSEL 2 PDSEL 1 PDSEL 0 VCC VCCA ODBSEL 1 ODBSEL 0 ODASEL 1 ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER BLOCK DIAGRAM Loop Filter 25MHz Output Divider QA Pullup PDSEL 2:0 00 = 25 (default) nQA 01 = 5 10 = 4 VCXO Input 11 = 2 CLK0 Phase Pre-Divider 0 Detector nCLK0 2 000 = 1 ODASEL 1:0 FemtoClock PLL 001 = 193 VCXO 625MHz 010 = 256 Charge CLK1 1 011 = 2430 Pump nCLK1 Output Divider 100 = 3125 QB VCXO Feedback Divider Pulldown 101 = 9720 00 = 25 (default) CLK SEL 3125 nQB 01 = 5 110 = 15625 10 = 4 111 = 19440 VCXO Jitter Attenuation PLL (default) 11 = 2 2 ODBSEL 1:0 ICS813252CKI-02 REVISION A AUGUST 4, 2016 2 2016 Integrated Device Technology, Inc. ISET LF0 LF1 XTAL IN XTAL OUT