VCXO Jitter Attenuator & 813N252I-04 FemtoClock NG Multiplier Datasheet General Description Features The 813N252I-04 is a PLL based synchronous multiplier that is Fourth generation FemtoClock Next Generation (NG) technology optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency One LVPECL output pair and one LVDS output pair Each output supports independent frequency selection at 25MHz, multiplication stages that are cascaded in series. The first stage is a 125MHz, 156.25MHz and 312.5MHz VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock NG frequency Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, requirements. Pre-divider and output divider multiplication ratios are 125MHz and 155.52MHz selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, Attenuates the phase jitter of the input clock by using a low-cost pullable fundamental mode VCXO crystal SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is FemtoClock NG frequency multiplier provides low jitter, high packaged in a space-saving 32-VFQFN package and supports frequency output industrial temperature range. Absolute pull range: 100ppm FemtoClock NG VCO frequency: 625MHz RMS phase jitter 125MHz, using a 25MHz crystal (12kHz 20MHz): 0.3ps (typical) 3.3V supply voltage -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment 32 31 30 29 28 27 26 25 LF1 1 24 VEE LF0 2 23 nQB ISET 3 22 QB VCCO VEE 4 21 CLK SEL 5 nQA 20 VCC 6 QA 19 RESERVED 7 VEE 18 VEE 8 ODASEL 0 17 9 10 11 12 13 14 15 16 813N252I-04 32 Lead VFQFN 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm EPad K Package Top View 2015 Integrated Device Technology, Inc. 1 Revision C, December 11, 2015 PDSEL 2 VCCX PDSEL 1 XTAL IN XTAL OUT PDSEL 0 VCC CLK0 VCCA nCLK0 VCC ODBSEL 1 ODBSEL 0 CLK1 ODASEL 1 nCLK1813N252I-04 Datasheet Block Diagram Loop Filter 25MHz LVDS Output Divider QA 3 Pullup PDSEL 2:0 00 = 25 (default) nQA 01 = 5 10 = 4 VCXO Input Pulldown 11 = 2 CLK0 Pre-Divider Phase PU/PD 0 Detector nCLK0 2 000 = 1 Pulldown FemtoClock NG ODASEL 1:0 001 = 193 VCXO PLL 010 = 256 Pulldown Charge CLK1 625MHz 1 011 = 2430 Pump PU/PD nCLK1 LVPECL Output Divider 100 = 3125 QB VCXO Feedback Divider Pulldown 101 = 9720 00 = 25 (default) CLK SEL 3125 nQB 01 = 5 110 = 15625 10 = 4 111 = 19440 VCXO Jitter Attenuation PLL (default) 11 = 2 2 Pulldown ODBSEL 1:0 2015 Integrated Device Technology, Inc. 2 Revision C, December 11, 2015 ISET LF0 LF1 XTAL IN XTAL OUT