FemtoClock NG Jitter Attenuator 8V19N470 Datasheet and Clock Synthesizer Description Features The 8V19N470 is a fully integrated FemtoClock NG jitter attenuator High-performance clock RF-PLL and clock synthesizer designed as a high-performance clock solution Optimized for low phase noise: 150dBc/Hz (1MHz offset for conditioning and frequency/phase management of wireless base 245.76MHz clock) station radio equipment boards. Dual-PLL architecture The device is optimized to deliver excellent phase noise 1st-PLL stage with external VCXO for clock jitter attenuation performance as required in GSM, WCDMA, LTE, LTE-A radio board 2nd-PLL stage with internal FemtoClock NG PLL at selectable implementations. A two-stage PLL architecture supports both jitter 2949.12MHz and 2400MHz 2500MHz VCO attenuation and frequency multiplication. The first stage PLL is the Five output channels with a total of 11 outputs, organized in: jitter attenuator and uses an external VCXO for best possible phase Two clock channels with two differential outputs noise characteristics. The second stage PLL locks on the VCXO-PLL Two clock channels with three differential outputs output signal and synthesizes the target frequency. This PLL has two VCO circuits at 2949.12MHz and 2400MHz2500MHz, respectively, One VCXO-PLL channel with one selectable LVDS/ two for enhanced frequency flexibility. LVCMOS outputs Each clock channel contains an integer output divider and a The device generates the output clock signals from the selected phase delay circuit with 512 steps of half of the VCO period VCO by frequency division. Four independent integer frequency Supported clock output frequencies include: dividers are available. Delay circuits can be used for achieving alignment and controlled phase delay between clock signals. The From VCO-0: 2949.12MHz, 1474.56MHz, 983.04MHz, two redundant inputs are monitored for activity. Four selectable clock 491.52MHz, 368.64MHz, 122.88MHz switching modes are provided to handle clock input failure scenarios. From VCO-1: 2457.6MHz, 1228.8MHz, 614.4MHz, 307.2MHz, Auto-lock, individually programmable output frequency dividers and 153.6, 76.8MHz or 625MHz, 500MHz, 312.5MHz, 250MHz, phase adjustment capabilities are added for flexibility. 156.25MHz, and 125MHz The device is configured through an SPI interface and reports PLL Low-power LVPECL/LVDS outputs support configurable signal lock and signal loss status in internal registers, PLL lock status is amplitude, DC and AC coupling and LVPECL, LVDS line also reported via two lock detect outputs. Internal status bit changes terminations techniques can also be reported via the nINT output. The device is ideal for Redundant input clock architecture driving converter circuits in wireless infrastructure, radar/imaging Two inputs and instrumentation/medical applications. The device is a member of Individual input signal monitor the high-performance clock family from IDT. Digital holdover Manual and automatic clock selection Typical Applications Hitless switching Low phase noise clock generation, specifically for jitter-sensitive Status monitoring and fault reporting ADC and DAC circuits Input signal status Wireless infrastructure applications: GSM, WCDMA, LTE, LTE-A Lock status of each individual PLL (two status pins) Ethernet Hold-over and reference loss status Mask-able status interrupt pin Voltage supply: Device core supply voltage: 3.3V Output supply voltage: 3.3V, 2.5V or 1.8V Digital control I/O voltage: 1.8V (3.3V tolerant) SPI control I/O voltage: 1.8V or 3.3V (selectable), 3.3V tolerant inputs when set to 1.8V Package: 81-FPBGA (8 8 1.35 mm, 0.8mm ball pitch) Temperature range: -40C to +85C 2017 Integrated Device Technology, Inc. 1 November 20, 20178V19N470 Datasheet Block Diagram Figure 1. Block Diagram VCXO-PLL VDD LCF Loop Filter R Z 4.7F C P CLK 0 C P , P Z V0 V1 Clock nCLK 0 CR0 Monitor P V BYPV CLK 1 FDF OSC and VDD LCF PFD P F nCLK 1 Selector CP LFV 2949.12MHz 4.7F nOSC PFD M V CP f x2 VCO CR1 EXT SEL 1:0 VCO 2400-2500MHz LFF DualFemtoClockNG FemtoClock NGPLLLoop C ZF Filter C PF M F Holdover RZF LFFR QCLK V nQCLK V VCXO-PLL Channel QCLK A0 N A nQCLK A0 CLKA (int) QCLK A1 nQCLK A1 QCLK A2 nQCLK A2 Channel A QCLK B0 N B nQCLK B0 CLKB (int) QCLK B1 nQCLK B1 QCLK B2 nQCLK B2 Channel B QCLK C0 N C nQCLK C0 CLKC (int) QCLK C1 nQCLK C1 Channel C RES CAL QCLK D0 N D nQCLK D0 2.8k CLKD (int) QCLK D1 nQCLK D1 Channel D nINT SDO SPI SDIO 1.8V/3.3V LOCK F SCLK nCS Register nRESET File LOCK V 2017 Integrated Device Technology, Inc. 2 November 20, 2017