5 4 3 2 1 Disclaimer: IDT is providing this schematic for reference purposes only. Although the schematic was taken from a known working design, it is being providedas i without any express or implied warranty of any kind. D D Power Supply XTAL Interface 12.8MHz TCXO/OCXO LED Status IN1 C C OUT1 Recovery Clock Sources IN3 8V89317 IN APLL1,2 OUT4 Jtag B B USB- I2C module uController A A TiTiTitttllleee SCHEMATIC, 8V89317EVB REV ASCHEMATIC, 8V89317EVB REV ASCHEMATIC, 8V89317EVB REV A SizSizSizeee Document NumberDocument NumberDocument Number RRReeevvv AAA Block DiagramBlock DiagramBlock Diagram 0.00.00.0 DDDaaattteee::: Friday, June 14, 2013Friday, June 14, 2013Friday, June 14, 2013 SSSheeheeheettt151515ofofof 5 4 3 2 1 ..........5 4 3 2 1 VDDA2 VDDA1 VDDD J1 1 2 TDI 3 4 C31 C86 C20 C105 C103 C137 C136 C175 C88 C87 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u TMS 5 6 TCK 7 8 9 10 VSSA VSSD TDO 11 12 TRST 13 14 15 16 17 18 19 20 D D CON20A VDDD VDDA2 VDDA1 Place close to the DUT pins CAP4~6 Place close to the C5 C19 C89 C104 DUT pins CAP1~3 0.1u 10u 0.1u 10u VSSA VSSA U13 VDDA E11 VDDA C11 C84 C85 VDDA 0.1u 0.1u D11 VSSA B11 F13 OUT4 VSSA OUT4 OUT4 VSSA OSCI A11 OSCI OSCI VDDDO RST H13 B14 RST RST VDDDO F12 VDDDO C11 F14 C6 C4 VSSDO 1nF B13 0.1u 0.1u VSSDO OUT1 POS J2 VSSDO OUT1 POS OUT1 NEG OUT1 POS VSSD J1 OUT1 NEG OUT1 NEG VCC3V3 2 IN1 H14 H3 VDDAO C C IN1 IN1 VDDAO IN2 J13 J3 IN2 IN2 VDDAO J14 H1 IN3 IN3 IN3 VDDAO C71 C72 OUT2 POS 0.1u 0.1u R73 L2 OUT2 POS OUT2 NEG OUT2 POS L1 100 OUT2 NEG OUT2 NEG SW DIP 8 J5 VDDAO VSSAO SW5 VDDAO K4 VDDAO 1 16 L3 VDDAO 2 15 C73 C74 OUT3 POS 3 14 N2 0.1u 0.1u OUT3 POS OUT3 POS 4 13 P2 OUT3 NEG VSSAO OUT3 NEG OUT3 NEG 5 12 J7 VDDAO Place the bypass caps close to the VDDAO DUT power/ground pins 6 11 K6 VDDAO I2C AD1 IN APLL1 POS 7 10 B5 P1 IN APLL1 POS IN APLL1 POS VDDAO I2C AD2 IN APLL1 NEG 8 9 A5 C75 C76 IN APLL1 NEG IN APLL1 NEG IN APLL2 POS N6 0.1u 0.1u IN APLL2 POS IN APLL2 POS IN APLL2 NEG P6 VSSAO IN APLL2 NEG IN APLL2 NEG M5 VDDAO RP1 VDDAO C3 M7 NC C3 VDDAO TP29 TP30 TP31 9 B1 P5 APLL1 LF1 VDDAO 8 VDDD C1 C77 C78 ISET APLL1 7 D8 0.1u 0.1u VDDD 1 6 D7 VSSD 5 M12 C7 C68 VSSAO NC M12 VDDDO 4 0.1u N12 C8 VDDDO APLL2 LF1 VSSDO GND 3 VSSD P13 ISET APLL2 2 E8 VDDD VDDD E7 C79 VSSD A1 0.1u 5.1K*8 APLL1 LF0 XTAL IN1 A3 P12 XTAL IN1 APLL2 LF0 XTAL OUT1 B3 A13 VSSDO XTAL OUT1 VC4 C69 XTAL IN2 TP8 P10 A9 XTAL IN2 VC0 0.1u XTAL OUT2 N10 XTAL OUT2 XTAL OUT1 C13 INT REQ XTAL OUT1 INT REQ XTAL IN1 I2C SDA JP8 VSSD VDDAO K14 XTAL IN1 I2C SDA I2C SDA XTAL OUT2 I2C AD1 I2C SDA L8 XTAL OUT2 I2C AD1 XTAL IN2 I2C AD2 I2C SCL L9 XTAL IN2 B I2C AD2 B C70 M1 K13 I2C SCL I2C Test Point I2C SCL VDDAO I2C SCL C164 M3 VSSAO B8 10u 0.1u TDO TDO A14 TRST GND TRST A12 TMS TMS VSSAO B10 TCK TCK A8 TDI TDI E9 IC1 D9 IC2 K8 G8 VSSD IC3 F2 VSSD G6 VDDA VSSD G1 C12 VSSD VDDA H9 D12 VSSD VDDA VSSD H7 B12 C80 C81 VSSD VSSA G10 E12 0.1u 0.1u VSSD VSSA F9 VSSD DPLL LOCK F7 J11 DPLL LOCK VSSA VSSD T0 LOCK C9 VDDA VDDA D10 VDDA G3 C10 VSSAO VSSA G4 E10 C82 C83 VSSAO VSSA G5 0.1u 0.1u VSSAO M2 E5 VSSAO VSSA H2 B2 VSSA VSSAO VSSA H4 D1 VSSAO VSSA F6 F4 VSSAO VSSA TP18 IDT8V89317 IN APLL1 POS TP19 A A VSSA IN APLL2 POS VSSAO TP33 TP32 TP4 TP5 TP6 TP7 TiTiTitttllleee SCHEMATIC, 8V89317 EVB REV A SizSizSizeee DocumDocumDocumententent Num Num Numberberber RRReeevvv CustomCustomCustom 8V893178V893178V89317 0.00.00.0 DDDaaattteee::: Friday, June 14, 2013Friday, June 14, 2013Friday, June 14, 2013 SSShhheeteeteet252525ofofof 5 4 3 2 1 D4 VSSA E3 VSSA J4 VSSAO H6 A4 VSSAO CAP1 K2 C4 VSSAO CAP2 K1 D3 VSSAO CAP3 H5 VSSAO K3 J10 VSSAO VDDA F3 P11 VSSAO VDDA E4 P14 VSSAO VDDA B4 P9 VSSAO VDDA D2 A2 VSSAO VDDA J6 C2 VSSAO VDDA J8 D5 VSSAO VDDA K5 F5 VSSAO VDDA K7 VSSAO K10 F1 VSSAO VDDD L4 G2 VSSAO VDDD L5 K9 VSSAO VDDD L6 F8 VSSAO VDDD L7 G7 VSSAO VDDD M4 G9 VSSAO VDDD M6 H10 VSSAO VDDD M8 H8 VSSAO VDDD M9 F10 VSSAO VDDD M10 VSSAO M11 L10 VSSAO CAP4 N1 L12 VSSAO CAP5 N3 L14 VSSAO CAP6 N5 VSSAO N13 L11 VSSAO VSSA P3 L13 VSSAO VSSA B9 VSSAO N9 VSSA N11 VSSA N14 VSSA J9 VSSA