DAC1408D750HN-C1 Renesas

DAC1408D750 Dual 14-bit DAC; up to 750 Msps; 2 , 4 or 8 interpolating with JESD204A interface Rev. 04 2 July 2012 Product data sheet 1. General description The DAC1408D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2 , 4 or 8 interpolating filters optimized for multi-carrier WCDMA transmitters. Because of its digital on-chip modulation, the DAC1408D750 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. The DAC1408D750 also includes a 2 , 4 or 8 clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current. The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum number of lanes of the DAC1408D750 is 4 and its maximum serial data rate is 3.125 Gbps. The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output clock period between several DAC devices. MDS incorporates modes: Master/slave and All slave mode. 2. Features and benefits Dual 14-bit resolution IMD3: 80 dBc; f = 737.28 Msps; s f = 140 MHz o 750 Msps maximum update rate ACPR: 71 dBc; two carriers WCDMA; f = 737.28 Msps; f =153.6 MHz s o Selectable 2 , 4 or 8 interpolation Typical 1.28 W power dissipation at 4 filters interpolation, PLL off and 740 Msps Input data rate up to 312.5 Msps Power-down mode and Sleep modes Very low-noise cap-free integrated PLL Differential scalable output current from 1.6 mA to 22 mA 32-bit programmable NCO frequency On-chip 1.29 V reference Four JESD204A serial input lanes External analog offset control (10-bit auxiliary DACs) 1.8 V and 3.3 V power supplies Internal digital offset control LVDS compatible clock inputs Inverse (sin x) / x function Integrated Device Technology DAC1408D750 2 , 4 or 8 interpolating DAC with JESD204A Twos complement or binary offset data Fully compatible SPI port format LMF = 421 or LMF = 211 support Industrial temperature range from 40 Cto+85 C Differential CML receiver with Integrated PLL can be bypassed embedded termination Synchronization of multiple DAC outputs Embedded complex modulator 3. Applications Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point to point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE) 4. Ordering information Table 1. Ordering information Type number Package Name Description Version DAC1408D750HN HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; SOT804-3 64 terminals; body 9 9 0.85 mm DAC1408D750 4 IDT 2012. All rights reserved. Product data sheet Rev. 04 2 July 2012 2 of 96