EL4511 Data Sheet November 12, 2010 FN7009.8 Super Sync Separator Features The EL4511 sync separator IC is designed for operation in Composite, component, HDTV, and PC signal-compatible the next generation of DTV, HDTV, and projector Tri-level & bi-level sync-compatible applications, as well as broadcast equipment and other Auto sync detection applications where video signals need to be processed. 150kHz max line rate The EL4511 accepts sync on green, separate sync, and H/V sync inputs, automatically selecting the relevant format. It is Low power also capable of detecting and decoding tri-level syncs used Small package outline with the latest HD systems. Unlike standard sync separators, the EL4511 can automatically detect the line rate and locks 3.3V and 5V operation to it, without the use of an external R resistor. SET Pb-Free Plus Anneal Available (RoHS Compliant) The EL4511 is available in a 24-pin QSOP package and Applications operates over the full 0C to 70C temperature range. HDTV/DTV analog inputs Ordering Information Video projectors PART TAPE & Computer monitors NUMBER PACKAGE REEL PKG. DWG. EL4511CU 24-Pin QSOP - MDP0040 Set top boxes EL4511CU-T7 24-Pin QSOP 7 MDP0040 Security video EL4511CU-T13 24-Pin QSOP 13 MDP0040 Broadcast video equipment EL4511CUZ 24-Pin QSOP - MDP0040 Pinout (See Note) (Pb-Free) EL4511 EL4511CUZ-T7 24-Pin QSOP 7 MDP0040 (24-PIN QSOP) (See Note) (Pb-Free) TOP VIEW EL4511CUZ-T13 24-Pin QSOP 13 MDP0040 (See Note) (Pb-Free) XTAL 1 24 XTALN NOTE: Intersil Pb-free plus anneal products employ special Pb-free VBLANK 2 23 ODD/EVEN material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and SYNCLOCK 3 22 VERTOUT compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow PDWN 4 21 HOUT temperatures that meet or exceed the Pb-free requirements of SDENB 5 20 BACKPORCH IPC/JEDEC J STD-020. SCL 6 19 SYNCOUT SDA 7 18 VCCD GNDD1 8 17 GNDD2 HIN 9 16 GNDA2 SYNCIN 10 15 VCCA2 VERTIN 11 14 VCCA1 LEVEL 12 13 GNDA1 1 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2002-2005, 2010. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303EL4511 Absolute Maximum Ratings (T = 25C) A Supply Voltage . (V to GND) +6V Storage Temperature Range -65C to +150C S Pin Voltage . GND - 0.3V, V +0.3V Operating Junction Temperature . 125C S V , V & V Must Be Same Voltage Ambient Operating Temperature . 0C to +70C CCA1 CCA2 CCD Power Dissipation . See Curves CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T J C A Electrical Specifications V = V = V = V = +5V, T = 25C, NTSC input signal on SYNCIN, no output loads, unless S CCA1 CCA2 CCD A otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT GENERAL ISD Digital Supply Current (Note 1) 15 20 mA Standby PDWN = V (Note 2) 4 20 A CCD ISA2 Rate Acquisition Oscillator Supply (Note 1) 3 20 mA Current Standby PDWN = V 2.5 20 A CCD ISA1 Analog Processing Supply Current (Note 1) 3 20 mA Standby PDWN = V (Note 2) 3 20 A CCD COMPOSITE SYNC INPUT AT SYNCIN V Sync Signal Amplitude AC coupled to SYNCIN pin (Notes 1 & 3) 140 600 mV SYNC V Slicing Level of Sync Signal After sync lock is attained, see description 50 % SLICE HORIZONTAL AND VERTICAL INPUT AT H , VERTIN IN H , V Slice Level of H and VERTIN 1.4 V SLICE SLICE IN T H Sync Width 312.8 % of H HINL (Bi-Level) time (Tri-Level) Minimum Sync Width 1.4 % of H time F H Sync Frequency 10.75 150 kHz HINH T V Sync Width 27 H lines VINL F V Sync Frequency 23 100 Hz VINH LOGIC OUTPUT SIGNALS, H , V , V , BACKPORCH, ODD/EVEN, SYNCLOCK OUT OUT BLANK O/P Logic Low State 1.6mA, V = 5V GNDD+0.4 V LOW CCD 1.6mA, V = 3.3V GNDD+0.5 CCD O/P Logic High State 1.6mA, V = 5V V -0.4 V HI CCD CCD 1.6mA, V = 3.3V V -0.5 CCD CCD Td H Timing Relative to Input See timing diagrams 1, 2, 3 & 4 HOUT OUT Td SYNCOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4 SYNCOUT Td BACKPORCH Timing Relative to See timing diagrams 1, 2, 3 & 4 BACKPORCH Input LEVEL OUTPUT DRIVER, LEVEL V 2 X Amplitude of V Refer to description of operation 1.9x 2.15x 2.4x LEVEL SYNC Z O/P Resistance of Driver Stage 450 LEVEL FN7009.8 2 November 12, 2010