User Guide 9FGV1005 PhiClock Evaluation Board Introduction The evaluation board is designed to help the customer evaluate the 9FGV1005 device. When the board is connected to a PC running IDT Timing Commander software through USB, the device can be configured and programmed to generate different combinations of frequencies. Board Overview Use Figure 1 and Table 1 to identify: power supply jacks, USB connector, input and output frequency SMA connectors. Figure 1. Evaluation Board Overview 10 9 8 7 6 11 12 1 2 3 4 5 2018 Integrated Device Technology, Inc. 1 February 28, 20189FGV1005 PhiClock Evaluation Board User Guide Table 1. Evaluation Board Pins and Functions Label Number Name On-board Connector Label Function 2 Alternative I C interface connector for Aardvark. 2 1I C Interface Connector J2 IDT Timing Commander can also use Aardvark. Connect this USB to your PC to run IDT Timing Commander. 2 USB Connector J6 The board can be powered from the USB port. Connect to 1.8V, 2.5V or 3.3V for the output voltage of 3 Output Power Supply Jack J3 the device. Connect to 1.8V, 2.5V or 3.3V for the core voltage of the 4 Core Power Supply Jack J4 device. 5 Ground Jack J5 Connect to ground of power supply. Can be a differential pair, or two single-ended outputs. 6 Differential Output 0 S3 and S4 Available logic types: LVCMOS, LVDS and LP-HCSL. Can be a differential pair, or two single-ended outputs. 7 Differential Output 1 S7 and S10 Available logic types: LVCMOS, LVDS and LP-HCSL. VDD REFP1, VDDO 0, VDDO 1, four-way headers Power Supply Voltage used to select a power supply voltage. Connect the 8 E1, E2, E3 Selector center pin to one of the 4 surrounding pins to select a voltage or a source. VDDA0, four-way headers used to select a power supply Power Supply Voltage 9 E4 voltage. Connect the center pin to one of the 4 Selector surrounding pins to select a voltage or a source. 10 Reference Output 0 S1 Reference or buffered output from the crystal. 2 I C bus enable access registers. 11 SEL I2C JP3 OTP bank CFG0 used to initialize RAM configuration registers. OTP bank CFG used to initialize RAM configuration 12 SCL, SDA/SEL0, SEL1 JP1, JP2 registers. Board Power Supply The evaluation board uses jumpers E1E4 to set the power supply voltages for various V pins. The 4-way jumpers can select 3 DD different voltages from regulators that use power from the USB port. Selection 2 is the jack for connecting a bench power supply. E1: Power supply for the REF outputs. The E1 voltage also determines the LVCMOS output levels of the REF0 and REF1 outputs. E2: Power supply for the OUT0 output driver. E3: Power supply for the OUT1 output driver. E4: Power supply for the analog (V ) and digital (V ) core V pins. DDA DDD DD See 9FGV1005 Evaluation Board Schematics (Figure 4Figure 7) for detailed information. 2018 Integrated Device Technology, Inc. 2 February 28, 2018