DATASHEET
HD-15530
FN2960
Rev 1.00
CMOS Manchester Encoder-Decoder
March 1997
Features Description
Support of MlL-STD-1553 The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 MBit/s
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
Sync Identification and Lock-In
sections, an Encoder and a Decoder. These sections
Clock Recovery
operate completely independent of each other, except for the
Master Reset functions.
Manchester II Encode, Decode
This circuit meets many of the requirements of MIL-STD-
Separate Encode and Decode
1553. The Encoder produces the sync pulse and the parity
Low Operating Power. . . . . . . . . . . . . . . . . .50mW at 5V
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decod-
Ordering Information
ing the data bits and checking parity.
PACKAGE TEMP. RANGE 1.25 MEGABIT/s PKG. NO.
This integrated circuit is fully guaranteed to support the
o o
CERDIP -40 C to +85 C HD1-15530-9 F24.6 1MHz data rate of MlL-STD-1553 over both temperature and
o o voltage. It interfaces with CMOS, TTL or N channel support
-55 C to +125 C HD1-15530-8
circuitry, and uses a standard 5V supply.
SMD# 7802901JA
o o The HD-15530 can also be used in many party line digital
CLCC -40 C to +85 C HD4-15530-9 J28.A
data communications applications, such as an environmen-
o o
-55 C to +125 C HD4-15530-8
tal control system driven from a single twisted pair cable of
SMD# 78029013A
fiber optic cable throughout the building.
o o
PDIP -40 C to +85 C HD3-15530-9 E24.6
Pinouts
HD-15530 (CERDIP, PDIP) HD-15530 (CLCC)
TOP VIEW TOP VIEW
VALID WORD 1 24 V
CC
ENCODER
2 23 ENCODER CLK
SHIFT CLK
TAKE DATA 3 22 SEND CLK IN
SERIAL DATA OUT 4 21 SEND DATA 4 3 2 1 28 27 26
DECODER SEND
20 SYNC SELECT 5 25
DECODER CLK 5
CLK DATA
BIPOLAR ZERO IN 6 19 ENCODER ENABLE
NC 6 24 NC
BIPOLAR ONE IN 7 18 SERIAL DATA IN
23 NC
NC 7
UNIPOLAR DATA IN 8 17 BIPOLAR ONE OUT
BIPOLAR SYNC
8 22
DECODER SHIFT CLK 9 16 OUTPUT INHIBIT
ZERO IN SELECT
COMMAND/ BIPOLAR
BIPOLAR ENCODER
10 15
9 21
DATA SYNC ZERO OUT
ONE IN ENABLE
DECODER RESET 11 14 6 OUT
UNIPOLAR SERIAL
10 20
DATA IN DATA IN
GND 12 13 MASTER RESET
DECODER
BIPOLAR
11
19
SHIFT CLK
ONE OUT
12 13 14 15 16 17 18
FN2960 Rev 1.00 Page 1 of 13
March 1997
COMMAND/
SERIAL
DATA SYNC
DATA OUT
DECODER
TAKE DATA
RESET
ENCODER
GND
SHIFT CLK
MASTER
VALID
RESET
WORD
V
6 OUT CC
BIPOLAR
ENCODER
ZERO OUT
CLK
SEND
OUTPUT
CLK IN
INHIBITHD-15530
Block Diagrams
ENCODER DECODER
GND
V
CC
12
8
24 3
UNIPOLAR
TAKE
MASTER RESET
DATA IN
13
OUTPUT DATA
7
TRANSITION CHARACTER
INHIBIT BIPOLAR
SEND CLK IN
22
16 FINDER IDENTIFIER
ONE IN
17 10
6 OUT
BIPOLAR
6 COMMAND/
BIPOLAR
2
14
CHARACTER ONE OUT
DATA SYNC
ZERO IN
FORMER
BIPOLAR
6 4 SERIAL
ZERO OUT
15 DATA OUT
BIT
ENCODER 1
5
PARITY
VALID
DECODER
CLK SYNCHRONIZER RATE
CHECK
WORD
CLK
23
CLK
BIT
9 DECODER
13
MASTER
18 19 20
COUNTER
SHIFT
2
RESET
21 CLK
SERIAL SYNC
DATA IN SELECT DECODER 11
BIT
SEND
RESET
COUNTER
DATA ENCODER
ENABLE
ENCODER
SHIFT CLK
Pin Description
PIN
NUMBER TYPE NAME SECTION DESCRIPTION
1 O VALID WORD Decoder Output high indicates receipt of a valid word, (valid parity and no Manches-
ter errors).
2 O ENCODER SHIFT Encoder Output for shifting data into the Encoder. The Encoder samples SDI on the
CLOCK low-to-high transition of Encoder Shift Clock.
3 O TAKE DATA Decoder Output is high during receipt of data after identification of a sync pulse and
two valid Manchester data bits.
4 O SERIAL DATA OUT Decoder Delivers received data in correct NRZ format.
5 I DECODER CLOCK Decoder Input drives the transition finder, and the synchronizer which in turn
supplies the clock to the balance of the decoder, input a frequency equal to
12X the data rate.
6 I BIPOLAR ZERO IN Decoder A high input should be applied when the bus is in its negative state. This pin
must be held high when the Unipolar input is used.
7 I BIPOLAR ONE IN Decoder A high input should be applied when the bus is in its positive state. This pin
must be held low when the Unipolar input is used.
8 I UNLPOLAR DATA IN Decoder With pin 6 high and pin 7 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
9 O DECODER SHIFT Decoder Output which delivers a frequency (DECODER CLOCK 12), synchro-
CLOCK nized by the recovered serial data stream.
10 O COMMAND SYNC Decoder Output of a high from this pin occurs during output of decoded data which
was preceded by a Command (or Status) synchronizing character. A low
output indicates a Data synchronizing character.
11 I DECODER RESET Decoder A high input to this pin during a rising edge of DECODER SHIFT CLOCK
resets the decoder bit counting logic to a condition ready for a new word.
12 I GROUND Both Ground Supply pin.
13 I MASTER RESET Both A high on this pin clears 2:1 counters in both Encoder and Decoder, and re-
sets the 6 circuit.
14 O 6 OUT Encoder Output from 6:1 divider which is driven by the ENCODER CLOCK.
15 O BIPOLAR ZERO OUT Encoder An active low output designed to drive the zero or negative sense of a
bipolar line driver.
16 I OUTPUT INHIBIT Encoder A low on this pin forces pin 15 and 17 high, the inactive states.
17 O BIPOLAR ONE OUT Encoder An active low output designed to drive the one or positive sense of a bipolar
line driver.
FN2960 Rev 1.00 Page 2 of 13
March 1997