OBSOLETE PRODUCT DATASHEET NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc ISL12025 FN6371 Rev 4.00 Real-Time Clock/Calendar with I2C Bus and EEPROM October 12, 2015 The ISL12025 device is a low power real-time clock with Features timing and crystal compensation, clock/calender, 64-bit Real-Time Clock/Calendar unique ID, power-fail indicator, two periodic or polled alarms, - Tracks Time in Hours, Minutes and Seconds intelligent battery backup switching, CPU Supervisor and - Day of the Week, Day, Month and Year integrated 512x8-bit EEPROM, in a 16 Bytes per page format. 64-Bit Unique ID Two Non-Volatile Alarms The oscillator uses an external, low-cost 32.768kHz crystal. - Settable on the Second, Minute, Hour, Day of the Week, The real-time clock tracks time with separate registers for Day or Month hours, minutes, and seconds. The device has calendar - Repeat Mode (Periodic Interrupts) registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year Automatic Backup to Battery or Super Cap correction. On-Chip Oscillator Compensation - Internal Feedback Resistor and Compensation Applications Capacitors - 64 Position Digitally Controlled Trim Capacitor Utility Meters - 6 Digital Frequency Adjustment Settings to 30ppm Audio/Video Components 512x8-Bits of EEPROM Modems - 16-Bytes Page Write Mode (32 total pages) Network Routers, Hubs, Switches, Bridges - 8 Modes of Block Lock Protection - Single Byte Write Capability Cellular Infrastructure Equipment High Reliability Fixed Broadband Wireless Equipment - Data Retention: 50 years Pagers/PDA - Endurance: 2,000,000 Cycles Per Byte POS Equipment 2 I C Interface Test Meters/Fixtures - 400kHz Data Transfer Rate Office Automation (Copiers, Fax) 800nA Battery Supply Current Home Appliances Package Options - 8 Ld SOIC and 8 Ld TSSOP Packages Computer Products Pb-Free (RoHS Compliant) Other Industrial/Medical/Automotive Ordering Information PART TEMP. NUMBER PART V RANGE PACKAGE PKG. RESET (Note) MARKING VOLTAGE (C) (Pb-Free) DWG. ISL12025IBZ* 12025 IBZ 2.63V -40 to +85 8 Ld SOIC M8.15 ISL12025IVZ* 2025 IVZ 2.63V -40 to +85 8 Ld TSSOP M8.173 No longer available or supported *Add -T suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6371 Rev 4.00 Page 1 of 28 October 12, 2015ISL12025 Pinouts Pin Descriptions ISL12025 PIN (8 LD SOIC) NUMBER TOP VIEW SY SOI TSS MB X1 V DD C OP OL BRIEF DESCRIPTION 1 8 X2 V BAT 2 1 3 X1 The X1 pin is the input of an inverting amplifier 7 and is intended to be connected to one pin of an SCL RESET 3 6 external 32.768kHz quartz crystal. X1 can also GND SDA 4 5 be driven directly from a 32.768kHz source. 2 4 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an ISL12025 external 32.768kHz quartz crystal. (8 LD TSSOP) TOP VIEW 35 RES RESET. This is a reset signal output. This signal ET notifies a host processor that the watchdog V BAT SCL 1 8 time period has expired or that the voltage has V SDA DD 2 7 dropped below a fixed V threshold. It is an TRIP GND X1 3 6 open drain active LOW output. Recommended X2 RESET value for the pull-up resistor is 5k . If unused, 4 5 connect to ground. 46 GN Ground. D 5 7 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. 6 8 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). 71 V This input provides a backup supply voltage to BA the device. V supplies power to the device in T BAT the event that the V supply fails. This pin DD should be tied to ground if not used. 82 V Power Supply. DD Block Diagram OSC COMPENSATION X1 TIMER TIME BATTERY V FREQUENCY 1Hz DD 32.768KHZ KEEPING SWITCH OSCILLATOR CALENDAR DIVIDER V CIRCUITRY BAT REGISTERS X2 LOGIC (SRAM) CONTROL/ STATUS CONTROL COMPARE SCL SERIAL REGISTERS REGISTERS ALARM DECODE INTERFACE LOGIC (EEPROM) (SRAM) DECODER ALARM REGS SDA (EEPROM) 8 4k EEPROM WATCHDOG LOW VOLTAGE ARRAY TIMER RESET RESET FN6371 Rev 4.00 Page 2 of 28 October 12, 2015 NO LONGER AVAILABLE OR SUPPORTED MASK