ISL22317 Precision Single Digitally Controlled Potentiometer (XDCP) Data Sheet April 15, 2010 FN6912.1 2 Low Noise, Low Power, I C Bus, 128 Taps Features The digitally controlled potentiometer is implemented with a Precision Digitally Controlled Potentiometer combination of resistor elements and CMOS switches. The - 99% Typical Accuracy Of Resistance Over Operational 2 position of the wiper is controlled by the user through the I C Conditions bus interface. The potentiometer has an associated volatile - Zero-Compensated Wiper Resistance Wiper Register (WR) and a non-volatile Initial Value Register Integrated Digitally Controlled Potentiometer (IVR) that can be directly written to and read by the user. The - 128-Tap Positions contents of the WR control the position of the wiper. At 2 power up, the device recalls the contents of the DCPs IVR -I C Serial Interface to the WR. - Pin Selectable Slave Address -10k, 50k and 100kTotal Resistance The highly precise ISL22317 features a low end-to-end - Monotonic Over-Temperature temperature coefficient of TC Ref 10ppm/C and precise - Non-Volatile EEPROM Storage of Wiper Position resistance selection. It maintains less than 1% typical - 0 to VCC Terminal Voltage variance from the ideal resistance at each wiper position providing 99% accuracy of selected resistance value. This Single 2.7V to 5.5V Supply highly accurate DCP eliminates the need for complex High Reliability algorithms to guarantee precision. The ISL22317 allows the - 50 Years Retention +55C user to dial in an accurate resistance and the EEPROM - 15 Years Retention +125C memory stores the set value for life, or until changed by the user. - 1,000,000 Cycles Endurance 3mmx3mm Thin DFN Package 0.75mm Max Thickness, An external 0.5% or better reference resistor must be 0.65mm Pitch attached to the ISL22317. The ISL22317 will mirror both the precise resistance and temperature coefficient of the Pb-Free (RoHS Compliant) external resistor. Applications The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of Setting Precise Current Values for DC Margining and applications including control, parameter adjustments, and Backlight Control signal processing. Replaces Complex Compensation Circuitry That Stores Values in Look-up Tables Needed for Precise Resistor Pinout Setting ISL22317 (10 LD TDFN) Setting Precise Resistance Values for Test and TOP VIEW Measurement Circuits Adjust Specific Resistances in Analog Circuits SCL VCC 1 10 Precise Calibration and Fine Tune-Up SDA 2 9 RH A1 RW 3 8 REF A 4 7 RL REF B GND 5 6 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. 2 I C Bus is a trademark owned by NXP Semiconductors Netherlands, B.V. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.ISL22317 Ordering Information PART NUMBER PART RESISTANCE OPTION TEMP. RANGE PACKAGE PKG. (Notes 1, 2, 3) MARKING (k) (C) (Pb-free) DWG. ISL22317TFRTZ 317T 100 -40 to +125 10 Ld TDFN L10.3x3B ISL22317UFRTZ 317U 50 -40 to +125 10 Ld TDFN L10.3x3B ISL22317WFRTZ 317W 10 -40 to +125 10 Ld TDFN L10.3x3B NOTES: 1. Add -TK suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL22317. For more information on MSL please see techbrief TB363. Block Diagram VCC SCL RH SDA POWER-UP, INTERFACE, RW EEPROM A1 AND CONTROL LOGIC REF A RL R REF 10k 0.5% External Resistor for W option, REF B or 50k 0.5% for U and T options respectively GND Pinout Pin Descriptions ISL22317 TDFN (10 LD TDFN) PIN SYMBOL DESCRIPTION TOP VIEW 2 1 SCL Open drain I C interface clock input 2 SCL VCC 2 SDA Open drain Serial data I/O for the I C interface 1 10 2 3 A1 Device address input for the I C interface SDA 2 9 RH 4 REF A Terminal A for an external reference resistor A1 3 8 RW 5 REF B Terminal B for an external reference resistor REF A 4 7 RL 6 GND Device ground pin REF B 5 6 GND 7 RL Low terminal of DCP 8 RW Wiper terminal of DCP 9 RH High terminal of DCP 10 VCC Power supply pin EPAD* Exposed Die Pad internally connected to GND *PCB thermal land for QFN/TDFN EPAD should be connected to GND plane or left floating. For more information refer to