ISL22326 Dual Digitally Controlled Potentiometers (XDCP) Data Sheet September 8, 2009 FN6176.2 2 Low Noise, Low Power, I C Bus, 128 Taps Features The ISL22326 integrates two digitally controlled potentiometers Two potentiometers in one package (XDCP) and non-volatile memory on a monolithic CMOS 128 resistor taps integrated circuit. 2 I C serial interface The digitally controlled potentiometers are implemented with - Three address pins, up to eight devices/bus a combination of resistor elements and CMOS switches. The Non-volatile storage of wiper position position of the wipers are controlled by the user through the 2 I C bus interface. Each potentiometer has an associated Wiper resistance: 70 typical V = 3.3V CC volatile Wiper Register (WR) and a non-volatile Initial Value Shutdown mode Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the Shutdown current 5A max wiper. At power-up the device recalls the contents of the two Power supply: 2.7V to 5.5V DCPs IVR to the corresponding WRs. 50k or 10k total resistance The DCPs can be used as three-terminal potentiometers or High reliability as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and - Endurance: 1,000,000 data changes per bit per register signal processing. - Register data retention: 50 years T < +55C 14 Ld TSSOP or 16 Ld QFN package Pb-free (RoHS compliant) Pinouts ISL22326 ISL22326 (14 LD TSSOP) (16 LD QFN) TOP VIEW TOP VIEW V 1 14 A1 CC SHDN 2 13 A0 16 15 14 13 RH0 RH1 3 12 1 12 RL0 RH0 RH1 4 11 RL1 RW0 5 RW1 10 2 11 RL1 RL0 6 A2 9 GND RW1 3 10 RW0 7 SCL 8 SDA 4 9 NC NC 576 8 Ordering Information PART NUMBER RESISTANCE OPTION TEMP. RANGE PACKAGE (Note) PART MARKING (k) (C) (Pb-free) PKG. DWG. ISL22326UFV14Z* 22326 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 ISL22326UFR16Z* 223 26UFZ 50 -40 to +125 16 Ld 4x4 QFN L16.4x4A ISL22326WFV14Z* 22326 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL22326WFR16Z* 223 26WFZ 10 -40 to +125 16 Ld 4x4 QFN L16.4x4A *Add -TK suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. A2 SHDN V SCL CC A1 SDA A0 GNDISL22326 Block Diagram V CC SCL RH1 POWER-UP SDA INTERFACE, 2 WR1 RW1 I C CONTROL A0 INTERFACE AND STATUS RL1 A1 LOGIC A2 RH0 RW0 WR0 NON- RL0 VOLATILE REGISTERS SHDN GND Pin Descriptions TSSOP PIN QFN PIN NUMBER NUMBER PIN NAME DESCRIPTION 115 V Power supply pin CC 2 16 SHDN Shutdown active low input 3 1 RH0 High terminal of DCP0 4 2 RL0 Low terminal of DCP0 5 3 RW0 Wiper terminal of DCP0 2 6 5 A2 Device address input for the I C interface 2 7 6 SCL Open drain I C interface clock input 2 8 7 SDA Open drain Serial data I/O for the I C interface 9 8 GND Device ground pin 10 10 RW1 Wiper terminal of DCP1 11 11 RL1 Low terminal of DCP1 12 12 RH1 High terminal of DCP1 2 13 13 A0 Device address input for the I C interface 2 14 14 A1 Device address input for the I C interface 4, 9 NC No connection EPAD* Exposed Die Pad internally connected to GND *Note: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to