ISL22326WM Dual Digitally Controlled Potentiometers (XDCP) Data Sheet November 11, 2011 FN6623.1 2 Low Noise, Low Power, I C Bus, 128 Taps Features The ISL22326WMVEP integrates two digitally controlled Specifications per DLA VID V62/08604-01XE potentiometers (XDCP) and non-volatile memory on a Full Mil-Temp Electrical Performance from -55C to +125C monolithic CMOS integrated circuit. Controlled Baseline with One Wafer Fabrication Site and The digitally controlled potentiometers are implemented with One Assembly/Test Site a combination of resistor elements and CMOS switches. The Full Homogeneous Lot Processing in Wafer Fab position of the wipers are controlled by the user through the 2 I C bus interface. Each potentiometer has an associated No Combination of Wafer Fabrication Lots in Assembly volatile Wiper Register (WR) and a non-volatile Initial Value Full Traceability Through Assembly and Test by Register (IVR) that can be directly written to and read by the Date/Trace Code Assignment user. The contents of the WR controls the position of the Enhanced Process Change Notification wiper. At power-up, the device recalls the contents of the two DCPs IVR to the corresponding WRs. Enhanced Obsolescence Management The DCPs can be used as three-terminal potentiometers or Eliminates Need for Up-Screening a COTS Component as two-terminal variable resistors in a wide variety of Two Potentiometers in One Package applications including control, parameter adjustments and signal processing. 128 Resistor Taps 2 I C Serial Interface Device Information - Three Address Pins, Up To Eight Devices/Bus The specifications for an Enhanced Product (EP) device are Non-volatile Storage of Wiper Position defined in a Vendor Item Drawing (VID), which is controlled by the Defense Logistics Agency (DLA). Hot-links to the Wiper Resistance: 70 Typical 3.3V applicable VID and other supporting application information Shutdown Mode are provided on our website. Shutdown Current 5A Max Pinout Power Supply: 2.7V to 5.5V ISL22326WMVEP (14 LD TSSOP) 10k Total Resistance TOP VIEW High Reliability V 14 1 A1 CC - Endurance: 1,000,000 Data Changes Per Bit Per 13 SHDN 2 A0 Register 12 RH1 RH0 3 - Register Data Retention: 4 - 10 years T +125C RL0 11 RL1 - 15 years T +90C 5 RW1 RW0 10 - 50 years T +55C 6 A2 9 GND SCL 7 14 Ld TSSOP 8 SDA Ordering Information TEMP. VENDOR PART NUMBER RESISTANCE OPTION RANGE PKG. (Notes 1, 2) VENDOR ITEM DRAWING PART MARKING (k) (C) PACKAGE DWG. ISL22326WMVEP V62/08604-01XE 22326 WMVEP 10 -55 to +125 14 Ld TSSOP M14.173 NOTES: 1. Add -TK suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Devices must be procured to the VENDOR PART NUMBER. CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2011. All Rights Reserved All other trademarks mentioned are the property of their respective owners.ISL22326WM Block Diagram V CC SCL RH1 SDA POWER-UP 2 WR1 RW1 I C INTERFACE, A0 INTERFACE CONTROL RL1 AND STATUS A1 LOGIC A2 RH0 RW0 WR0 NON- RL0 VOLATILE REGISTERS SHDN GND Pin Descriptions TSSOP PIN SYMBOL DESCRIPTION 1V Power supply pin CC 2SHDN Shutdown active low input 3 RH0 High terminal of DCP0 4 RL0 Low terminal of DCP0 5 RW0 Wiper terminal of DCP0 2 6 A2 Device address input for the I C interface 2 7 SCL Open drain I C interface clock input 2 8 SDA Open drain Serial data I/O for the I C interface 9 GND Device ground pin 10 RW1 Wiper terminal of DCP1 11 RL1 Low terminal of DCP1 12 RH1 High terminal of DCP1 2 13 A0 Device address input for the I C interface 2 14 A1 Device address input for the I C interface FN6623.1 2 November 11, 2011