Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP) ISL23345 Features Four potentiometers per package The ISL23345 is a volatile, low voltage, low noise, low power, 256 tap, quad digitally controlled potentiometer (DCP) with an 256 resistor taps 2 I C Bus interface. It integrates four DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. 10k, 50k or 100k total resistance 2 I C serial interface Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The - No additional level translator for low bus supply position of the wipers are controlled by the user through the - Three address pins allow up to eight devices per bus 2 I C bus interface. Each potentiometer has an associated Maximum supply current without serial bus activity volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly (standby) written to and read by the user. The contents of the WRi - 5A V and V = 5V controls the position of the wiper. When powered on, the wiper CC LOGIC of each DCP will always commence at mid-scale (128 tap - 2A V and V = 1.7V CC LOGIC position). Shutdown Mode - Forces the DCP into an end-to-end open circuit and RWi is The low voltage, low power consumption, and small package connected to RLi internally of the ISL23345 make it an ideal choice for use in battery operated equipment. In addition, the ISL23345 has a V - Reduces power consumption by disconnecting the DCP LOGIC pin allowing down to 1.2V bus operation, independent from the resistor from the circuit V value. This allows for low logic levels to be connected CC Power supply directly to the ISL23345 without passing through a voltage -V = 1.7V to 5.5V analog power supply CC level shifter. 2 -V = 1.2V to 5.5V I C bus/logic power supply LOGIC The DCP can be used as a three-terminal potentiometer or as a Wiper resistance: 70 typical V = 3.3V CC two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Power-on preset to mid-scale (128 tap position) Extended industrial temperature range: -40C to +125C Applications 20 Ld TSSOP or 20 QFN packages Power supply margining Trimming sensor circuits Pb-free (RoHS compliant) Gain adjustment in battery powered instruments RF power amplifier bias compensation 10000 V REF 8000 RH1 6000 - V REF M 1 DCP 4000 RW1 of + ISL23345 ISL28114 2000 RL1 0 0 64 128 192 256 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP FIGURE 2. V ADJUSTMENT REF POSITION, 10k DCP June 21, 2011 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas Inc. 2011. All Rights Reserved FN7872.0 Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners RESISTANCE ( )ISL23345 Block Diagram V V LOGIC CC RH0 WR0 RW0 VOLATILE SCL REGISTER POWER UP SDA RL0 INTERFACE RH1 I/O LEVEL CONTROL A0 WR1 BLOCK SHIFTER AND RW1 VOLATILE A1 STATUS REGISTER LOGIC A2 RL1 RH2 WR2 RW2 VOLATILE REGISTER RL2 RH3 WR3 RW3 VOLATILE REGISTER RL3 GND Pin Configurations Pin Descriptions ISL23345 TSSOP QFN SYMBOL DESCRIPTION (20 LD TSSOP) 1 19 RL0 DCP0 low terminal TOP VIEW 220 RW0 DCP0 wiper terminal RL0 1 20 RL3 31 V Analog power supply. RW0 2 19 RW3 CC Range 1.7V to 5.5V V 3 18 RH3 CC 4 2 RH0 DCP0 high terminal RH0 4 17 RL2 RL1 5 16 RW2 5 3 RL1 DCP1 low terminal RW1 6 15 RH2 64 RW1 DCP1 wiper terminal RH1 7 14 SCL 7 5 RH1 DCP1 high terminal GND 8 13 SDA 8 6 GND Ground pin V 9 12 A2 LOGIC 2 A0 10 11 A1 97 V I C bus /logic supply. Range 1.2V to 5.5V LOGIC 10 8 A0 Logic Pin - Hardwire slave address pin for 2 I C serial bus. ISL23345 Range: V or GND LOGIC (20 LD QFN) 11 9 A1 Logic Pin - Hardwire slave address pin for TOP VIEW 2 I C serial bus. Range: V or GND LOGIC 12 10 A2 Logic Pin - Hardwire slave address pin for 20 19 18 17 2 I C serial bus. V 1 6 RH3 Range: V or GND 16 CC LOGIC 13 11 SDA Logic Pin - Serial bus data input/open 15 RL2 RH0 2 drain output RW2 3 14 RL1 14 12 SCL Logic Pin - Serial bus clock input RH2 4 13 RW1 15 13 RH2 DCP2 high terminal 12 SCL 5 RH1 16 14 RW2 DCP2 wiper terminal 11 SDA GND 6 17 15 RL2 DCP2 low terminal 18 16 RH3 DCP3 high terminal 78 9 10 19 17 RW3 DCP3 wiper terminal 20 18 RL3 DCP3 low terminal FN7872.0 2 June 21, 2011 V RW0 LOGIC RL0 A0 A1 RL3 A2 RW3