DATASHEET ISL23445 FN7874 Rev 0.00 Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP) June 21, 2011 The ISL23445 is a volatile, low voltage, low noise, low power, 256 Features tap, quad digitally controlled potentiometer (DCP) with an SPI Four potentiometers per package Bus interface. It integrates four DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. 256 resistor taps Each digitally controlled potentiometer is implemented with a 10k 50k or 100k total resistance combination of resistor elements and CMOS switches. The SPI serial interface position of the wipers are controlled by the user through the - No additional level translator for low bus supply SPI bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly - Daisy Chaining of multiple DCPs written to and read by the user. The contents of the WRi Maximum supply current without serial bus activity controls the position of the wiper. When powered on, the wiper (standby) of each DCP will always commence at mid-scale (128 tap - 5A V and V = 5V CC LOGIC position). -2uA V and V = 1.7V CC LOGIC The low voltage, low power consumption, and small package Shutdown Mode of the ISL23445 make it an ideal choice for use in battery - Forces the DCP into an end-to-end open circuit and RWi is operated equipment. In addition, the ISL23445 has a V LOGIC connected to RLi internally pin allowing down to 1.2V bus operation, independent from the - Reduces power consumption by disconnecting the DCP V value. This allows for low logic levels to be connected CC resistor from the circuit directly to the ISL23445 without passing through a voltage level shifter. Power supply -V = 1.7V to 5.5V analog power supply CC The DCP can be used as a three-terminal potentiometer or as a -V = 1.2V to 5.5V SPI bus/logic power supply two-terminal variable resistor in a wide variety of applications LOGIC including control, parameter adjustments, and signal processing. Wiper resistance: 70 typical V = 3.3V CC Applications Power-on preset to mid-scale (128 tap position) Power supply margining Extended industrial temperature range: -40C to +125C Trimming sensor circuits 20 Ld TSSOP or 20 Ld QFN packages Gain adjustment in battery powered instruments Pb-free (RoHS compliant) RF power amplifier bias compensation 10000 VREF 8000 RH1 6000 - VREF M 1 DCP RW1 4000 of + ISL23445 2000 ISL28114 RL1 0 0 64 128 192 256 TAP POSITION (DECIMAL) FIGURE 2. V ADJUSTMENT FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP REF POSITION, 10k DCP FN7874 Rev 0.00 Page 1 of 20 June 21, 2011 NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ISL23425 RESISTANCE ()ISL23445 Block Diagram V V LOGIC CC RH0 WR0 RW0 VOLATILE SDI POWER UP REGISTER RL0 SDO INTERFACE RH1 I/O CONTROL LEVEL SCK WR1 BLOCK AND SHIFTER RW1 VOLATILE STATUS CS REGISTER LOGIC RL1 RH2 WR2 RW2 VOLATILE REGISTER RL2 RH3 WR3 RW3 VOLATILE REGISTER RL3 GND Pin Configurations Pin Descriptions ISL23445 TSSOP QFN SYMBOL DESCRIPTION (20 LD TSSOP) 1 19 RL0 DCP0 low terminal TOP VIEW 2 20 RW0 DCP0 wiper terminal RL0 1 20 RL3 31 V Analog power supply. RW0 2 19 RW3 CC Range 1.7V to 5.5V V 3 18 RH3 CC 42 RH0 DCP0 high terminal RH0 4 17 RL2 RL1 5 16 RW2 5 3 RL1 DCP1 low terminal RW1 6 15 RH2 6 4 RW1 DCP1 wiper terminal RH1 7 14 SCK 75 RH1 DCP1 high terminal GND 8 13 SDO 8, 12 6, 10 GND Ground pin V 9 12 GND LOGIC SDI 10 11 CS 97 V SPI bus /logic supply LOGIC Range 1.2V to 5.5V ISL23445 10 8 SDI Logic Pin - Serial bus data input (20 LD QFN) TOP VIEW 11 9 CS Logic Pin - Active low chip select 13 11 SDO Logic Pin - Serial bus data output (configurable) 20 19 18 17 14 12 SCK Logic Pin - Serial bus clock input V 1 6 RH3 16 CC 15 13 RH2 DCP2 high terminal RL2 RH0 2 15 16 14 RW2 DCP2 wiper terminal 14 RW2 17 15 RL2 DCP2 low terminal RL1 3 18 16 RH3 DCP3 high terminal RH2 4 13 RW1 19 17 RW3 DCP3 wiper terminal SCK 5 12 RH1 20 18 RL3 DCP3 low terminal 11 SDO GND 6 78 9 10 FN7874 Rev 0.00 Page 2 of 20 June 21, 2011 V RW0 LOGIC RL0 SDI RL3 CS GND RW3