DATASHEET ISLA214P50 FN7571 Rev.4.0 14-Bit, 500MSPS ADC Jul 6, 2021 The ISLA214P50 is a 14-bit, 500MSPS analog-to-digital Features converter designed with the Renesas proprietary FemtoCharge Automatic fine interleave correction calibration technology on a standard CMOS process. The ISLA214P50 is Single supply 1.8V operation part of a pin-compatible portfolio of 12 to 16-bit A/Ds with maximum sample rates ranging from 130MSPS to 500MSPS. Clock duty cycle stabilizer 75fs clock jitter The device utilizes two time-interleaved 250MSPS unit ADCs to achieve the ultimate sample rate of 500MSPS. A single 700MHz bandwidth 500MHz conversion clock is presented to the converter, and all Programmable built-in test patterns interleave clocking is managed internally. The proprietary Multi-ADC support Interleave Engine (I2E) performs automatic correction of offset, gain, and sample time mismatches between the unit - SPI programmable fine gain and offset control ADCs to optimize performance. - Support for multiple ADC synchronization A Serial Peripheral Interface (SPI) port allows for extensive - Optimized output timing configurability of the A/D. The SPI also controls the interleave Nap and sleep modes correction circuitry, allowing the system to issue offline and - 200s sleep wake-up time continuous calibration commands as well as configure many Data output clock dynamic parameters. DDR LVDS-compatible or LVCMOS outputs Digital output data is presented in selectable LVDS or CMOS Selectable clock divider formats. The ISLA214P50 is available in a 72 Ld QFN package with an exposed paddle. Operating from a 1.8V supply, Applications performance is specified across the full industrial temperature Radar array processing range (-40C to +85C). Software defined radios Broadband communications Key Specifications High-performance data acquisition SNR at 500MSPS Communications test equipment -72.7dBFS f = 30MHz IN -70.6dBFS f = 363MHz IN SFDR at 500MSPS -84dBc f = 30MHz IN -76dBc f = 363MHz IN Total power consumption = 835mW at 500MSPS Pin-Compatible Family SPEED MODEL RESOLUTION (MSPS) CLKP CLKOUTP CLOCK ISLA216P25 16 250 MANAGEMENT CLKN CLKOUTN ISLA216P20 16 200 ISLA216P13 16 130 14-BIT D 13:0 P SHA 250 MSPS ISLA214P50 14 500 ADC D 13:0 N ISLA214P25 14 250 VREF ORP VINP Gain, Offset DIGITAL ORN and Skew IE ERROR ISLA214P20 14 200 VINN Adjustments CORRECTION ISLA214P13 14 130 14-BIT ISLA212P50 12 500 SHA 250 MSPS ADC ISLA212P25 12 250 VREF + VCM SPI ISLA212P20 12 200 CONTROL ISLA212P13 12 130 FN7571 Rev.4.0 Page 1 of 38 Jul 6, 2021 2011 Renesas Electronics AVSS AVDD NAPSLP RESETN CLKDIV CLKDIVRSTP CLKDIVRSTN CSB SCLK SDIO SDO RLVDS OVSS OVDDISLA214P50 Table of Contents Ordering Information 4 Pin Configuration - LVDS MODE 4 Pin Descriptions - 72 Ld QFN, LVDS Mode . 5 Pin Configuration - CMOS MODE . 6 Pin Descriptions - 72 Ld QFN, CMOS Mode 6 Absolute Maximum Ratings . 8 Thermal Information . 8 Electrical Specifications . 8 Digital Specifications . 10 I2E Specifications 11 Timing Diagrams . 12 Switching Specifications 13 Typical Performance Curves . 14 Theory of Operation . 17 Functional Description . 17 Power-On Calibration . 17 User Initiated Reset 18 Temperature Calibration . 19 Analog Input 19 Clock Input . 20 Jitter . 20 Voltage Reference . 20 Digital Outputs 20 Power Dissipation . 21 Nap/Sleep 21 Data Format 21 I2E Requirements and Restrictions . 22 Overview . 22 Active Run State 22 Power Meter 22 FS/4 Filter 22 Nyquist Zones . 22 Configurability and Communication 22 Clock Divider Synchronous Reset . 23 Serial Peripheral Interface 25 SPI Physical Interface 25 SPI Configuration 25 Device Information 26 Device Configuration/Control 26 Address 0x60-0x64: I2E Initialization . 28 Global Device Configuration/Control . 28 SPI Memory Map . 31 Equivalent Circuits . 35 A/D Evaluation Platform . 36 Layout Considerations 36 Split Ground and Power Planes 36 Clock Input Considerations 36 Exposed Paddle . 36 Bypass and Filtering . 36 LVDS Outputs . 36 LVCMOS Outputs 36 Unused Inputs 36 Definitions 36 FN7571 Rev.4.0 Page 2 of 38 Jul 6, 2021