OT N RECOMMENDED FOR NEW DESIGNS EC R OMMENDED REPLACEMENT PART ISL62884C DATASHEET ISL6261A FN6354 Rev 3.00 Single-Phase Core Regulator for IMVP-6 Mobile CPUs November 5, 2009 The ISL6261A is a single-phase buck regulator Features implementing lntel IMVP-6 protocol, with embedded gate Precision single-phase CORE voltage regulator drivers. lntel Mobile Voltage Positioning (IMVP) is a smart - 0.5% system accuracy over temperature voltage regulation technology effectively reducing power - Enhanced load line accuracy dissipation in lntel Pentium processors. 3 Internal gate driver with 2A driving capability The heart of the ISL6261A is the patented R Technology, Intersils Robust Ripple Regulator modulator. Compared with Microprocessor voltage identification input 3 the traditional multi-phase buck regulator, the R - 7-Bit VID input Technology has faster transient response. This is due to - 0.300V to 1.500V in 12.5mV steps 3 the R modulator commanding variable switching frequency - Support VID change on-the-fly during a load transient. Multiple current sensing schemes supported The ISL6261A provides three operation modes: the - Lossless inductor DCR current sensing Continuous Conduction Mode (CCM), the Diode Emulation - Precision resistive current sensing Mode (DEM) and the Enhanced Diode Emulation Mode Thermal monitor (EDEM). To boost battery life, the ISL6261A changes its operation mode based on CPU mode signals DPRSLRVR Power monitor indicating CPU instantaneous power and DPRSTP , and the FDE pin setting, to maximize the User programmable switching frequency efficiency. In CPU active mode, the ISL6261A commands the CCM operation. When the CPU enters deeper sleep Differential remote voltage sensing at CPU die mode, the ISL6261A enables the DEM to maximize the Overvoltage, undervoltage, and overcurrent protection efficiency at light load. Asserting the FDE pin of the ISL6261A in CPU deeper sleep mode will enable the EDEM Pb-free (RoHS compliant) to further decrease the switching frequency at light load and Ordering Information increase the regulator efficiency. TEMP. A 7-bit Digital-to-Analog Converter (DAC) allows dynamic PART NUMBER PART RANGE PACKAGE PKG. adjustment of the core output voltage from 0.300V to 1.500V. (Notes 2, 3) MARKING (C) (Pb-Free) DWG. The ISL6261A has 0.5% system voltage accuracy over ISL6261ACRZ ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6 temperature. ISL6261ACRZ-T* ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6 A unity-gain differential amplifier provides remote voltage (Note 1) Tape and Reel sensing at the CPU die. This allows the voltage on the CPU ISL6261AIRZ 6261A IRZ -40 to +100 40 Ld 6x6 QFN L40.6x6 die to be accurately measured and regulated per lntel IMVP-6 specification. Current sensing can be implemented ISL6261AIRZ-T* 6261A IRZ -40 to +100 40 Ld 6x6 QFN L40.6x6 (Note 1) Tape and Reel through either lossless inductor DCR sensing or precise resistor sensing. If DCR sensing is used, an NTC thermistor NOTES: network will thermally compensates the gain and the time 1. Please refer to TB347 for details on reel specifications. constant variations caused by the inductor DCR change. 2. These Intersil Pb-free plastic packaged products employ special Pb- free material sets, molding compounds/die attach materials, and The ISL6261A provides the power monitor function through 100% matte tin plate plus anneal (e3 termination finish, which is the PMON pin. PMON output is a high-bandwidth analog RoHS compliant and compatible with both SnPb and Pb-free voltage signal representing the CPU instantaneous power. soldering operations). Intersil Pb-free products are MSL classified at The power monitor function can be used by the system to Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. optimize the overall power consumption, extending battery 3. For Moisture Sensitivity Level (MSL), please see device information run time. page for ISL6261A. For more information on MSL please see techbrief TB363. FN6354 Rev 3.00 Page 1 of 34 November 5, 2009ISL6261A Pinout ISL6261A (40 LD QFN) TOP VIEW 40 39 38 37 36 35 34 33 32 31 FDE 1 30 VID2 PMON 2 29 VID1 RBIAS 3 28 VID0 VR TT 4 27 VCCP NTC 5 26 LGATE GND PAD (BOTTOM) SOFT 6 25 VSSP OCSET 7 24 PHASE VW 8 23 UGATE COMP 9 22 BOOT FB 10 21 NC 11 12 13 14 15 16 17 18 19 20 FN6354 Rev 3.00 Page 2 of 34 November 5, 2009 VDIFF PGOOD VSEN 3V3 RTN CLK EN DROOP DPRSTP DFB DPRSLPVR VO VR ON VSUM VID6 VIN VID5 VSS VID4 VDD VID3