DATASHEET ISL62773 FN8263 Rev 1.00 Multiphase PWM Regulator for AMD Fusion Desktop CPUs Using SVI 2.0 Dec 16, 2015 The ISL62773 is fully compliant with AMD Fusion SVI 2.0 and Features provides a complete solution for desktop microprocessor and Supports AMD SVI 2.0 serial data bus interface graphics processor core power. The ISL62773 controller supports two Voltage Regulators (VRs) with three integrated gate drivers - Serial VID clock frequency range 100kHz to 25MHz and two optional external drivers for maximum flexibility. The Dual output controller with integrated drivers Core VR can be configured for 3-, 2-, or 1-phase operation while - Two dedicated core drivers the Northbridge VR supports 2- or 1-phase configurations. The two - One programmable driver for either core or Northbridge VRs share a serial control bus to communicate with the AMD CPU and achieve lower cost and smaller board area compared with Precision voltage regulation two-chip solutions. - 0.5% system accuracy over-temperature The PWM modulator is based on Intersils Robust Ripple - 0.5V to 1.55V in 6.25mV steps Regulator R3 technology. Compared to traditional modulators, - Enhanced load line accuracy the R3 modulator can automatically change switching frequency for faster transient settling time during load transients and Supports multiple current sensing methods improved light-load efficiency. - Lossless inductor DCR current sensing - Precision resistor current sensing The ISL62773 has several other key features. Both outputs support DCR current sensing with a single NTC thermistor for Programmable 1-, 2- or 3-phase for the core output and 1- or DCR temperature compensation or accurate resistor current 2-phase for the Northbridge output sensing. Both outputs utilize remote voltage sense, adjustable Adaptive body diode conduction time reduction switching frequency, OC protection and power-good. Superior noise immunity and transient response Applications Output current monitor and thermal monitor AMD Fusion CPU/GPU core power Differential remote voltage sensing Desktop computers High efficiency across entire load range Programmable slew rate, VID offset, droop and switching frequency on both outputs OCP/WOC, OVP, PGOOD and thermal monitor Small footprint 48 Ld 6x6 QFN Package - Pb-free (RoHS compliant) Core Performance 100 1.12 90 1.10 80 V = 8V IN 1.08 70 V = 12V IN 60 1.06 V = 8V IN V = 19V IN 50 1.04 40 V = 12V 1.02 IN 30 1.00 20 V = 19V IN 10 0.98 V CORE = 1.1V OUT V CORE = 1.1V OUT 0 0.96 0 5 10 15 20 25 30 35 40 45 50 55 0 5 10 15 20 25 30 35 40 45 50 55 I (A) I (A) OUT OUT FIGURE 2. V vs LOAD FIGURE 1. EFFICIENCY vs LOAD OUT FN8263 Rev 1.00 Page 1 of 37 Dec 16, 2015 EFFICIENCY (%) V (A) OUTISL62773 Table of Contents Simplified Application Circuit for High Power CPU Core . 3 AMD Serial VID Interface 2.0 21 Pre-PWROK Metal VID . 21 Simplified Application Circuit with 3 Internal Drivers Used SVI Interface Active . 22 for Core . 4 VID-on-the-Fly Transition . 22 Simplified Application Circuit for Mid-Power CPUs SVI Data Communication Protocol . 22 2+1 Configuration . 5 SVI Bus Protocol 25 Power States and Telemetry 25 Simplified Application Circuit for Low Power CPUs Dynamic Load Line Slope Trim 26 1+1 Configuration . 6 Dynamic Offset Trim . 26 Pin Configuration 8 Protection Features 26 Pin Descriptions . 8 Overcurrent 26 Current-Balance 26 Ordering Information .10 Undervoltage . 26 Absolute Maximum Ratings 11 Overvoltage 26 Thermal Monitor NTC, NTC NB . 27 Thermal Information 11 Fault Recovery 27 Recommended Operating Conditions .11 Interface Pin Protection 27 Electrical Specifications 11 Key Component Selection . 28 Gate Driver Timing Diagram 13 Inductor DCR Current-Sensing Network 28 Resistor Current-Sensing Network . 30 Theory of Operation .14 Overcurrent Protection . 30 Multiphase R3 Modulator . 14 Load Line Slope 30 Diode Emulation and Period Stretching . 15 Compensator . 31 Channel Configuration . 15 Current Balancing . 31 Power-On Reset . 15 Thermal Monitor Component Selection . 32 Start-Up Timing . 16 Layout Guidelines 32 Voltage Regulation and Load Line Implementation . 16 PCB Layout Considerations . 32 Differential Sensing 17 Phase Current Balancing . 17 Revision History . 36 Modes of Operation 19 About Intersil 36 Dynamic Operation 20 FB2 Function . 20 Package Outline Drawing . 37 Adaptive Body Diode Conduction Time Reduction 20 Resistor Configuration Options .20 VR Offset Programming 20 Floating DriverX and PWM Y Configuration 21 VID-on-the-Fly Slew Rate Selection . 21 CCM Switching Frequency 21 FN8263 Rev 1.00 Page 2 of 37 Dec 16, 2015