DATASHEET ISL62881, ISL62881B FN6924 Rev 3.00 Single-Phase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs June 16, 2011 The ISL62881 is a single-phase PWM buck regulator for Features miroprocessor or graphics processor core power supply. It uses an Precision Core Voltage Regulation integrated gate driver to provide a complete solution. The PWM modulator of ISL62881 is based on Intersil s Robust Ripple - 0.5% System Accuracy Over-Temperature 3 Regulator (R ) technology. Compared with traditional - Enhanced Load Line Accuracy 3 modulators, the R modulator commands variable switching Voltage Identification Input frequency during load transients, achieving faster transient - 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps response. With the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. - Supports VID Changes On-The-Fly The ISL62881 can be configured as CPU or graphics Vcore Supports Multiple Current Sensing Methods controller and is fully compliant with IMVP-6.5 specifications. It - Lossless Inductor DCR Current Sensing responds to DPRSLPVR signals by entering/exiting diode - Precision Resistor Current Sensing emulation mode. It reports the regulator output current through the IMON pin. It senses the current by using either discrete Superior Noise Immunity and Transient Response resistor or inductor DCR whose variation over-temperature can Current Monitor be thermally compensated by a single NTC thermistor. It uses Differential Remote Voltage Sensing differential remote voltage sensing to accurately regulate the processor die voltage. The adaptive body diode conduction High Efficiency Across Entire Load Range time reduction function minimizes the body diode conduction Integrated Gate Driver loss in diode emulation mode. User-selectable overshoot Split LGATE Driver to Increase Light-Load Efficiency (for reduction function offers an option to aggressively reduce the ISL62881B) output capacitors as well as the option to disable it for users concerned about increased system thermal stress. Adaptive Body Diode Conduction Time Reduction Maintaining all the ISL62881 functions, the ISL62881B offers User-selectable Overshoot Reduction Function VR TT function for thermal throttling control. It also offers the Capable of Disabling the Droop Function split LGATE function to further improve light load efficiency. Audio-filtering for GPU Application Small Footprint 28 Ld 4x4 TQFN Package Pb-Free (RoHS Compliant) Applications Notebook Computers Ordering Information PART NUMBER PART TEMP. RANGE PACKAGE PKG. (Notes 1, 2, 3) MARKING (C) (Pb-Free) DWG. ISL62881HRTZ 628 81HRTZ -10 to +100 28 Ld 4x4 TQFN L28.4x4 ISL62881BHRTZ 62881B HRTZ -10 to +100 32 Ld 5x5 TQFN L32.5x5E NOTES: 1. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62881, ISL62881B. For more information on MSL please see techbrief TB363. FN6924 Rev 3.00 Page 1 of 35 June 16, 2011ISL62881, ISL62881B Pin Configurations ISL62881 ISL62881B (28 LD TQFN) (32 LD TQFN) TOP VIEW TOP VIEW 28 27 26 25 24 23 22 32 31 30 29 28 27 26 25 VID1 CLK EN 1 21 VID1 PGOOD 1 24 PGOOD 2 20 VID0 RBIAS 2 23 VID0 VCCP RBIAS 3 19 VR TT 3 22 VCCP VW 4 18 LGATE GND PAD NTC 4 21 LGATEb GND PAD (BOTTOM) VSSP COMP 5 17 (BOTTOM) GND 5 20 LGATEa FB 6 16 PHASE VW 6 19 VSSP VSEN 7 15 UGATE COMP 7 18 PHASE 8 9 10 11 12 13 14 FB 8 17 UGATE 9 10 11 1213 1415 16 Pin Function Descriptions COMP GND (Bottom Pad) This pin is the output of the error amplifier. Also, a resistor across this Signal common of the IC. Unless otherwise stated, signals are pin and GND adjusts the overcurrent threshold. referenced to the GND pin. FB CLK EN This pin is the inverting input of the error amplifier. Open drain output to enable system PLL clock goes active 13 switching cycles after V is within 10% of V . core boot VSEN Remote core voltage sense input. Connect to microprocessor die. PGOOD Power-Good open-drain output indicating when the regulator is RTN able to supply regulated voltage. Pull-up externally with a 680 Remote voltage sensing return. Connect to ground at resistor to VCCP or 1.9k to 3.3V. microprocessor die. RBIAS ISUM- and ISUM+ A resistor to GND sets internal current reference. A 147k Droop current sense input. resistor sets the controller for CPU core application and a 47k resistor sets the controller for GPU core application. VDD 5V bias power. VR TT Thermal overload output indicator. VIN Battery supply voltage, used for feed-forward. NTC Thermistor input to VR TT circuit. IMON An analog output. IMON outputs a current proportional to the VW regulator output current. A resistor from this pin to COMP programs the switching frequency (8k gives approximately 300kHz). BOOT Connect an MLCC capacitor across the BOOT and the PHASE pins. The boot capacitor is charged through an internal boot FN6924 Rev 3.00 Page 2 of 35 June 16, 2011 P DPRSL VR VR ON VID6 V 5 ID VID4 VID3 VID2 CLK EN DPRSLPVR VR ON VID6 VID5 VID4 VID3 RTN ISUM- ISUM+ VDD VIN IMON BOOT VSEN RTN ISUM- ISUM+ VDD VIN IMON BOOT VID2