NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc DATASHEET ISL6363 FN6898 Rev 1.00 Multiphase PWM Regulator for VR12 Desktop CPUs Sep 5, 2013 Fully compliant with VR12 specifications, the ISL6363 Features provides a complete solution for microprocessor core and Serial Data Bus (SVID) graphics power supplies. It provides two Voltage Regulators (VRs) with three integrated gate drivers. The first output (VR1) Dual Outputs: can be configured as a 4, 3, 2 or 1-phase VR while the second - Configurable 4, 3, 2 or 1-phase for the 1st Output with 2 output (VR2) is a 1-phase VR. The two VRs share a serial control Integrated Gate Drivers bus to communicate with the CPU and achieve lower cost and - 1-phase for the 2nd Output with Integrated Gate Driver smaller board area compared with a two-chip approach. Precision Core Voltage Regulation Based on Intersils Robust Ripple Regulator R3 Technology, - 0.5% System Accuracy Over-Temperature the PWM modulator, compared to traditional modulators, has - Enhanced Load Line Accuracy faster transient settling time, variable switching frequency during load transients and has improved light load efficiency PS2 Compensation and High Frequency Load Transient with its ability to automatically change switching frequency. Compensation Differential Remote Voltage Sensing The ISL6363 has several other key features. Both outputs support DCR current sensing with a single NTC thermistor for Lossless Inductor DCR Current Sensing DCR temperature compensation or accurate resistor current Programmable V Voltage at Start-up BOOT sensing. Both outputs come with remote voltage sensing, programmable V voltage, serial bus address, IMAX, TMAX, Resistor Programmable Address, IMAX, TMAX for Both BOOT adjustable switching frequency, OC protection and separate Outputs power-good indicators. To reduce output capacitors, the Adaptive Body Diode Conduction Time Reduction ISL6363 also has an additional compensation function for PS1/2 mode and high frequency load transient compensation. Applications VR12 Desktop Computers Related Literature ISL6363EVAL1Z User Guide 1.15 1.10 1.7m LOADLINE V CORE 50mV/DIV 1.05 1.1V - PS1 1.00 1.1V - PS0 COMP 0.95 1V/DIV 65A STEP LOAD 0.90 0 1V/DIV 5 1015 20 253035 40 45 5055 6065 70 7580 85 2s/DIV I (A) OUT FIGURE 2. ACCURATE LOADLINE, V vs I FIGURE 1. FAST TRANSIENT RESPONSE CORE OUT FN6898 Rev 1.00 Page 1 of 32 Sep 5, 2013 V (V) COREISL6363 Ordering Information PART NUMBER TEMP. RANGE PACKAGE PKG. (Notes 1, 2, 3) PART MARKING (C) (Pb-Free) DWG. ISL6363CRTZ ISL6363 CRTZ 0 to +70 48 Ld 6x6 TQFN L48.6x6 ISL6363IRTZ ISL6363 IRTZ -40 to +85 48 Ld 6x6 TQFN L48.6x6 NOTES: 1. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6363. For more information on MSL please see techbrief TB363. Pin Configuration ISL6363 (48 LD TQFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 SCOMP 1 36 PHASEG PGOOD 2 35 UGATEG Temporary Pinout VCC 3 34 BOOTG ISUMP Subject to Change LGATEG 4 33 ISUMN 5 32 PVCCG GND PAD ISEN1 6 31 VR HOT (BOTTOM) ISEN2 7 30 NTCG ISEN3 8 29 ISUMNG ISEN4 9 28 ISUMPG VSEN 10 27 RTNG PSICOMP FBG 11 26 RTN 12 25 COMPG 13 14 15 16 17 18 19 20 21 22 23 24 Pin Descriptions ISL6363 SYMBOL DESCRIPTION Bottom GND Common ground signal of the IC. Unless otherwise stated, signals are referenced to the GND pin. The pad should also be Pad used as the thermal pad for heat dissipation. 1 SCOMP This pin is a placeholder for potential future functionality. This pin can be left floating. 2 PGOOD Power-good open-drain output indicating when VR1 is able to supply a regulated voltage. Pull-up externally with a 680 resistor to +5V or 1k to +3.3V. 3 VCC +5V bias supply pin. Connect a high quality 0.1F capacitor from this pin to GND and place it as close to the pin as possible. A small resistor (2.2 for example) between the +5V supply and the decoupling capacitor is recommended. 4, 5 ISUMP, VR1 current sense input pins for current monitoring, droop current and overcurrent detection. ISUMN 6 ISEN1 VR1 phase 1 current sense input pin for phase current balancing. 7 ISEN2 VR1 phase 2 current sense input pin for phase current balancing. 8 ISEN3 VR1 phase 3 current sense input pin for phase current balancing. FN6898 Rev 1.00 Page 2 of 32 Sep 5, 2013 ADDR FB PHASE1 COMP UGATE1 VW BOOT1 NTC LGATE1 IMON VR ON PVCC LGATE2 SDA BOOT2 ALERT UGATE2 SCLK PHASE2 PGOODG PWM3 IMONG PWM4 VWG