DATASHEET ISL6535 FN9255 Rev 3.00 Synchronous Buck Pulse-Width Modulator (PWM) Controller March 3, 2016 The ISL6535 is a high performance synchronous controller for Features demanding DC/DC converter applications. It provides Operates from +12V input overcurrent fault protection and is designed to safely start-up into prebiased output loads. Excellent output voltage regulation - 0.597V internal reference The output voltage of the converter can be precisely regulated to as low as 0.597V, with a maximum tolerance of 1% over - 1% over the commercial temperature range the commercial temperature range, and 1.5% over the - 1.5% over the industrial temperature range industrial temperature range. Simple single-loop control design The ISL6535 provides simple, single feedback loop, voltage - Voltage-mode PWM control mode control with fast transient response. It includes a Fast transient response triangle wave oscillator that is adjustable from below 50kHz to over 1.5MHz. Full (0% to 100%) PWM duty cycle support is - High-bandwidth error amplifier provided. - Full 0% to 100% duty ratio - Leading and falling edge modulation The error amplifier features a 15MHz gain bandwidth product and 6V/s slew rate, which enables high converter bandwidth Small converter size for fast transient performance. - Constant frequency operation The ISL6535 s overcurrent protection monitors the current by - Oscillator programmable from 50kHz to over 1.5MHz using the r of the upper MOSFET, which eliminates the DS(ON) 12V high-speed MOSFET gate drivers need for a current sensing resistor. - 2.0A source/3A sink at 12V low-side gate drive Pin Configurations - 1.25A source/2A sink at 12V high-side gate drive ISL6535 (14 LD SOIC) - Drives two N-channel MOSFETs TOP VIEW Overcurrent fault monitor RT 1 14 VCC - High-side MOSFETs r sensing DS(ON) OCSET 2 13 PVCC - Reduced ~120ns blanking time SS 3 12 LGATE Converter can source and sink current COMP 4 11 PGND Soft-start done and an external reference pin for tracking FB 5 10 BOOT applications are available in the QFN package EN 6 9 UGATE Pin compatible with ISL6522 GND 7 8 PHASE Supports start-up into prebiased loads Pb-free (RoHS compliant) ISL6535 (16 LD QFN) TOP VIEW Applications Power Supply for some Pentium, PowerPC, as well as graphic CPUs High-power 12V input DC/DC regulators 16 15 14 13 Low-voltage distributed power supplies SS 1 12 PVCC COMP 2 11 LGATE PAD FB 3 10 PGND EN 4 9 BOOT 576 8 FN9255 Rev 3.00 Page 1 of 15 March 3, 2016 REFIN SSDONE GND OCSET PHASE RT UGATE VCCISL6535 Pin Descriptions PIN PIN SOIC QFN PIN NAME DESCRIPTION 1 14 RT This pin provides oscillator switching frequency adjustment. By placing a resistor (R ) from RT this pin to GND, the switching frequency is set from between 200kHz and 1.5MHz according Equation 1: 6500 ------------------------------------------------------- R k 1.3k RT (R to GND) FkHz 200kHz RT s (EQ. 1) Alternately ISL6535s switching frequency can be lowered from 200kHz to 50kHz by connecting the RT pin with a resistor to VCC according to Equation 2: 55000 ------------------------------------------------------- R k + 70k RT (R to VCC) 200kHz FkHz RT s (EQ. 2) 2 15 OCSET The current limit is programmed by connecting this pin with a resistor and capacitor to the drain of the high-side MOSEFT. A 200A current source develops a voltage across the resistor, which is then compared with the voltage developed across the high-side MOSFET. A blanking period of 120ns is provided for noise immunity. 3 1 SS Connect a capacitor from this pin to ground. This capacitor, along with an internal 30A current source, sets the soft-start interval of the converter. 4 2 COMP COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are 53 FB used to compensate the voltage-control feedback loop of the converter. 6 4 EN This pin is a TTL compatible input. Pull this pin below 0.8V to disable the converter. In shutdown the soft-start pin is discharged and the UGATE and LGATE pins are held low. 7 6 GND Signal ground for the IC. All voltage levels are measured with respect to this pin. 8 7 PHASE This pin connects to the source of the high-side MOSFET and the drain of the low-side MOSFET. This pin represents the return path for the high-side gate driver. During normal switching, this pin is used for high-side current sensing. 9 8 UGATE Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. 10 9 BOOT This pin provides bias to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-channel MOSFET. 11 10 PGND This is the power ground connection. Tie the lower MOSFET source and board ground to this pin. 12 11 LGATE Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. 13 12 PVCC Provide a 12V 10% bias supply for the lower gate drive to this pin. This pin should be bypassed with a capacitor to PGND. 14 13 VCC Provide a 12V bias supply for the chip to this pin. The pin should be bypassed with a capacitor to GND. - 5 REFIN Upon enable if REFIN is less than 2.2V, the external reference pin is used as the control reference instead of the internal 0.597V reference. An internal 6A pull-up to 5V is provided for disabling this functionality. - 16 SSDONE Provides an open-drain signal at the end of soft-start. - PAD EPAD The exposed pad is at GND potential, but does not conduct current the GND and PGND pins must be used for bias current. The pad should be tied to a GND plane with as many thermal vias as possible, for optimal thermal performance. FN9255 Rev 3.00 Page 2 of 15 March 3, 2016