ISL6559CBZ Renesas

ISL6559 Data Sheet December 29, 2004 FN9084.8 Multi-Phase PWM Controller Features Multi-Phase Power Conversion The ISL6559 provides core-voltage regulation by driving 2 to - 2, 3 or 4 Phase Operation 4 interleaved synchronous-rectified buck-converter channels Active Channel Current Balancing in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output Precision r Current Sharing DS(ON) ripple currents. The reduction in ripple results in lower - Lossless component cost, reduced dissipation, and a smaller -Low Cost implementation area. Input Voltage: 12V or 5V Bias Precision CORE Voltage Regulation The ISL6559 uses cost and space-saving r sensing DS(ON) -1% System Accuracy Over Temperature for channel current balance, active voltage positioning, and - Differential Remote Output Voltage Sensing over-current protection. Output voltage is monitored by an - Programmable Reference Offset internal differential remote sense amplifier. A high-bandwidth Microprocessor Voltage Identification Input error amplifier drives the output voltage to match the - 5-Bit VID Input programmed 5-bit DAC reference voltage. The resulting - 0.800V to 1.550V in 25mV Steps compensation signal guides the creation of pulse width - Dynamic VID Technology modulated (PWM) signals to control companion Intersil Programmable Droop Voltage MOSFET drivers. The OFS pin allows direct offset of the Fast Transient Recovery Time DAC voltage from 0V to 50mV using a single external resistor. The entire system is trimmed to ensure a system Over Current Protection accuracy of 1% over temperature. Digital Soft Start Threshold Sensitive Enable Input Outstanding features of this controller IC include TM High Ripple Frequency (160kHz to 4MHz) Dynamic VID technology allowing seamless on-the-fly VID QFN Package: changing without the need of any external components. - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat Output voltage droop or active voltage positioning is No Leads - Package Outline optional. When employed, it allows the reduction in size and - Near Chip Scale Package footprint, which improves PCB cost of the output capacitors required to support load efficiency and has a thinner profile transients. A threshold-sensitive enable input allows the use of an external resistor divider for start-up coordination with Pb-Free Available (RoHS Compliant) Intersil MOSFET drivers or any other devices powered from Applications a separate supply. AMD Hammer Family Processor Voltage Regulator Superior over-voltage protection is achieved by gating on the Low Output Voltage, High Current DC-DC Converters lower MOSFET of all phases to crowbar the output voltage. Voltage Regulator Modules An optional second crowbar on V , formed with an external IN MOSFET or SCR gated by the OVP pin, is triggered when Pinouts an over-voltage condition is detected. Under-voltage ISL6559CB (28 LEAD SOIC) ISL6559CR (32 LEAD QFN) conditions are detected, but PWM operation is not disrupted. TOP VIEW TOP VIEW Over-current conditions cause a hiccup-mode response as GND 1 28 EN the controller repeatedly tries to restart. After a set number OVP 2 27 FS/DIS of failed startup attempts, the controller latches off. A power VID4 3 26 PGOOD 32 31 30 29 28 27 26 25 good logic signal indicates when the converter output is VID2 1 24 PWM4 VID3 4 25 PWM4 between the UV and OV thresholds. VID2 5 24 ISEN4 VID1 2 23 ISEN4 VID1 6 23 ISEN1 VID0 3 22 ISEN1 VID0 7 22 PWM1 NC 4 21 PWM1 OFS 8 21 PWM2 OFS 5 20 PWM2 COMP 9 20 GND COMP 6 19 GND FB 10 19 ISEN2 FB 7 18 ISEN2 IOUT 11 18 ISEN3 NC 8 17 ISEN3 VDIFF 12 17 PWM3 910 11 1213 14 1516 13 16 VCC VSEN RGND 14 15 GND NC = NO CONNECT CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 321-724-7143 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002-2004. All Rights Reserved. Dynamic VID is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. IOUT VID3 VDIFF NC VSEN VID4 RGND OVP GND GND GND EN VCC FS/DIS PWM3 PGOOD350mV ISL6559 Ordering Information Ordering Information (Continued) PART TEMP. (C) PACKAGE PKG. DWG. PART TEMP. (C) PACKAGE PKG. DWG. ISL6559CB 0 to 70 28 Ld SOIC M28.3 ISL6559CR-T 32 Ld 5x5 QFN Tape and Reel ISL6559CBZ* 0 to 70 28 Ld SOIC (Pb-free) M28.3 ISL6559CRZ-T* 32 Ld 5x5 QFN Tape and Reel (Pb-free) ISL6559CB-T 28 Ld SOIC Tape and Reel NOTE: * Intersil Pb-free products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate ISL6559CBZ-T* 28 Ld SOIC Tape and Reel (Pb-free) termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are ISL6559CR 0 to 70 32 Ld 5x5 QFN L32.5x5 MSL classified at Pb-free peak reflow temperatures that meet or ISL6559CRZ* 0 to 70 32 Ld 5x5 QFN (Pb-free) L32.5x5 exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram PGOOD VCC EN FS/DIS 1.23V VID4 OSCILLATOR 6V AND SAWTOOTH VID3 DYNAMIC POR AND VID VID2 SOFT START DAC VID1 UV PWM1 VID0 + + - PWM2 + E/A FB - + PWM3 + COMP - + PWM4 x 0.1 + OFS - 100 A + OVP VDIFF OV 2.2V I1 VSEN ISEN1 90A DIFF OC RGND + I2 CURRENT ISEN2 SENSE + AVERAGE IOUT 1/N & + PHASE I3 ISEN3 DETECT + I4 ISEN4 N PHASES GND FN9084.8 2 December 29, 2004 - +