ISL6556B Data Sheet December 28, 2004 FN9097.4 Optimized Multi-Phase PWM Controller Features with 6-Bit DAC and Programmable Internal Precision Multi-Phase Core Voltage Regulation Temperature Compensation for VR10.X - Differential Remote Voltage Sensing Application - 0.5% System Accuracy Over Temperature and Life The ISL6556B controls microprocessor core voltage - Adjustable Reference-Voltage Offset regulation by driving up to 4 synchronous-rectified buck Precision r Current Sensing DS(ON) channels in parallel. Multi-phase buck converter architecture - Integrated Programmable Temperature Compensation uses interleaved timing to multiply channel ripple frequency - Accurate Load-Line Programming and reduce input and output ripple currents. - Accurate Channel-Current Balancing The ISL6556B utilizes r current sensing in each DS(ON) - Low-Cost, Lossless Current Sensing phase for adaptive voltage positioning (droop), channel- Internal Shunt Regulator for 5V or 12V Biasing current balancing, and overcurrent protection. To ensure the accuracy of droop, a programmable internal temperature Microprocessor Voltage Identification Input compensation function is implemented to nullify the effect of - Dynamic VID Technology r temperature sensitivity. DS(ON) - 6-Bit VID Input - 0.8375V to 1.600V in 12.5mV Steps A unity gain, differential amplifier is provided for remote voltage sensing. Any potential difference between remote and local Threshold Enable Function for Precision Sequencing grounds can be eliminated using the remote-sense amplifier. Overcurrent Protection The precision threshold-sensitive enable input is available to accurately coordinate the startup of the ISL6556B with Intersil Overvoltage Protection MOSFET driver IC. Dynamic-VID technology allows - No Additional External Components Needed seamless on-the-fly VID changes. The offset pin allows accurate - OVP Pin to drive optional Crowbar Device voltage offset settings that are independent of VID setting. The 2, 3, or 4 Phase Operation up to 1.5MHz per Phase ISL6556B uses 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor. QFN Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Ordering Information Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint Improves PART NUMBER TEMP. (C) PACKAGE PKG. DWG. PCB Efficiency, Thinner in Profile ISL6556BCB* 0 to 70 28 Ld SOIC M28.3 Pb-free Available (RoHS Compliant) ISL6556BCBZ* 0 to 70 28 Ld SOIC (Pb-free) M28.3 (Note) ISL6556BCBZA 0 to 70 28 Ld SOIC Tape and M28.3 -T (Note) Reel (Pb-free) ISL6556BCR* 0 to 70 32 Ld 5x5B QFN L32.5x5B ISL6556BCRZ* 0 to 70 32 Ld 5x5B QFN L32.5x5B (Note) (Pb-free) * Add -T suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 321-724-7143 Intersil (and design) is a registered trademark of Intersil Americas Inc. Dynamic VID is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002-2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.ISL6556B Pinouts 32 LEAD QFN 28 LEAD SOIC TOP VIEW TOP VIEW FS OVP 1 28 PGOOD 27 EN 2 32 31 30 29 28 27 26 25 26 VID4 3 VCC VID3 PWM4 1 24 25 PWM4 VID3 4 VID2 24 ISEN4 VID2 2 23 ISEN4 5 23 ISEN2 VID1 6 VID1 3 22 ISEN2 VID0 22 PWM2 7 VID0 4 21 PWM2 PWM1 VID12.5 8 21 ISEN1 OFS 9 20 VID12.5 5 20 PWM1 10 19 ISEN3 TCOMP OFS 6 19 ISEN1 REF 11 18 PWM3 TCOMP 7 18 GND FB 12 17 GND COMP 13 16 RGND REF 8 17 ISEN3 VDIFF 14 15 VSEN 9 10 11 12 1314 1516 FN9097.4 2 December 28, 2004 OFSOUT VID4 FB PGOOD COMP OVP VDIFF FS VSEN GND RGND ENLL GND EN PWM3 VCC