DATASHEET ISL6617 FN7564 Rev 0.00 PWM Doubler with Phase Shedding Function and Output Monitoring Feature February 4, 2010 The ISL6617 utilizes Intersils proprietary Phase Features Doubler scheme to modulate two-phase power trains Proprietary Phase Doubler scheme with Phase with single PWM input. It doubles the number of Shedding Function (Patent Pending) phases that Intersils multi-phase controllers ISL63xx can support. When the enable pin (EN PH SYNC) is Enhanced Light to Full Load Efficiency pulled low, the PWM input is pulled high. This simplifies Double or Quadruple Phase Count the phase shedding implementation for some Intersil Patented Current Balancing with DCR Current controllers (VR10, VR11, VR11.1, and VR12 family) Sensing and Adjustable Gain that can disable the respective and higher phase(s) by Current Monitoring Output (IOUT) to Simplify pulling the respective PWM line high. System Interface and Layout The ISL6617 is designed to minimize the number of Triple-Level Enable Input for Mode Selection analog signals that interface between the controller Dual PWM Output Drives for Two Synchronous and drivers in high phase count scalable applications. Rectified Bridges with Single PWM Input The common COMP signal, which is usually seen in Channel Synchronization and Two Interleaving conventional cascaded configuration, is not required Options this improves noise immunity and simplifies the layout. Tri-State PWM Input and Outputs for Output Stage Furthermore, the ISL6617 provides low part count and Shutdown low cost advantage over the conventional cascaded technique. Phase Enable Input and PWM Forced High Output to Interface with Intersils Controller for Phase By cascading the ISL6617 with another ISL6617 or Shedding ISL6611A, it can quadruple the number of phases that Overvoltage Protection Intersils multi-phase controllers ISL63xx can support. Dual Flat No-Lead (DFN) Package The ISL6617 also features Tri-State input and outputs - Near Chip-Scale Package Footprint Improves that recognize a high-impedance state, working PCB Utilization, Thinner Profile together with Intersil multiphase PWM controllers and - Pb-Free (RoHS Compliant) driver stages to prevent negative transients on the controlled output voltage when operation is suspended. Related Literature This feature eliminates the need for the schottky diode Technical Brief TB363 Guidelines for Handling and that may be utilized in a power system to protect the Processing Moisture Sensitive Surface Mount load from excessive negative output voltage damage. Devices (SMDs) Applications High Current Low Voltage DC/DC Converters High Frequency and High Efficiency VRM and VRD High Phase Count and Phase Shedding Applications 5V PWM Input Integrated Power Stage or DrMOS Pin Configuration ISL6617 (10 LD DFN) TOP VIEW ISENA+ 1 10 PWMA ISENA- 2 9 VCC 11 PWMIN 3 8 IOUT GND ISENB+ 4 7 EN PH SYNC ISENB- 5 6PWMB FN7564 Rev 0.00 Page 1 of 15 February 4, 2010ISL6617 Functional Pin Descriptions PIN PIN SYMBOL FUNCTION 1 ISENA+ Output of the differential amplifier for Channel A. Connect a resistor on this pin to the negative rail of the sensed voltage to set the current gain. 2 ISENA- Input of the differential amplifier for Channel A. Typically, the positive rail of sensed voltage via DCR sensing network connects to this node. 3 PWMIN The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels are effectively modulated. The PWM signal can enter three distinct states during operation, see Operation section for further details. Connect this pin to the PWM output of the controller. The pin is pulled to VCC when EN PH SYNC is low. 4 ISENB+ Output of the differential amplifier for Channel B. Connect a resistor on this pin to the negative rail of the sensed voltage to set the current gain. 5 ISENB- Input of the differential amplifier for Channel B. Typically, the positive rail of sensed voltage via DCR sensing network connects to this node. 6 PWMB PWM output of Channel B with Tri-state feature. 7 EN PH SYNC Driver Enable and Mode Selection Input. See Enable and Mode Operation for more details. 8 IOUT Current monitoring Output. It sources out the average current of both Channel A and B. 9 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic capacitor from this pin to GND. 10 PWMA PWM output of Channel A with Tri-state feature. 11 GND Bias and reference ground. All signals are referenced to this node. Place a high quality low ESR ceramic capacitor from this pin to VCC. Connect this pad to the power ground plane (GND) via thermally enhanced connection. Block Diagram VCC 55k ISENA- PWMIN CHANNEL A ISENA+ 48k PWMA CONTROL LOGIC PWMB EN PH SYNC ISENB- CHANNEL B GND ISENB+ CURRENT IOUT BALANCE BLOCK FN7564 Rev 0.00 Page 2 of 15 February 4, 2010