DATASHEET ISL6731A, ISL6731B FN8582 Rev 1.00 Power Factor Correction Controllers February 13, 2015 The ISL6731A and ISL6731B are active power factor Features correction (PFC) controller ICs that use a boost topology. The Reduced component size requirements controllers are suitable for AC/DC power systems up to 2kW and over the universal line input. - Enables smaller, thinner AC/DC adapters - Choke and cap size can be reduced The ISL6731A and ISL6731B operate in Continuous Current - Lower cost of materials Mode (CCM). Accurate input current shaping is achieved with a current error amplifier. A patent pending breakthrough Excellent power factor and THD over line and load negative capacitance technology minimizes zero crossing - CCM mode with negative capacitance generator for distortion and reduces the magnetic components size. The smaller EMI filter and improved performance small external components result in lower design cost without - Built-in current amplifier with flexibility of gain change sacrificing performance. Better light-load efficiency The internally clamped 12.5V gate driver delivers 1.5A peak - Automatic pulse skipping with programmable threshold current to the external power MOSFET. The ISL6731A and ISL6731B provide a highly reliable system that is fully - Programmable or automatic shutdown protected. Protection features include cycle-by-cycle Highly reliable design overcurrent, over power limit, over-temperature, input - Cycle-by-cycle current limit brownout, output overvoltage and undervoltage protection. - Input average power limit The ISL6731A and ISL6731B provide excellent power - OVP and OTP protection efficiency and transitions into a power saving skip mode - Input brownout protection during light load conditions, thus improving efficiency automatically. The ISL6731A and ISL6731B can be shut down Small 14 Ld SOIC package by pulling the FB pin below 0.5V or grounding the BO pin. Applications Two switching frequency options are provided. The ISL6731B switches at 62kHz, and the ISL6731A switches at 124kHz. Desktop computer AC/DC adaptor Laptop computer AC/DC adaptor Related Literature TV AC/DC power supply AN1884, ISL6731AEVAL1Z and ISL6731BEVAL1Z: Boost AC/DC brick converters CCM PFC for 300W Universal Input Adaptor AN1885, ISL6731AEVAL2Z and ISL6731BEVAL2Z: High Performance Boost CCM PFC Front End for Server Power Applications 100 V I + V LINE V OUT 95 90 85 ISL6731A, SKIP VCC 80 ISEN GATE ICOMP OVP ISL6731A, NON-SKIP 75 ISL6731A VIN FB 70 COMP GND 65 BO SKIP VREG 60 0 20 40 60 80 100 OUTPUT POWER (%) FIGURE 1. TYPICAL APPLICATION FIGURE 2. PFC EFFICIENCY FN8582 Rev 1.00 Page 1 of 20 February 13, 2015 EFFICIENCY (%)ISL6731A, ISL6731B Pin Configuration ISL6731A, ISL6731B (14 LD SOIC) TOP VIEW NC 1 14 GATE GND 2 NC 13 ISEN 3 12 VCC ICOMP 4 11 VREG VIN 5 10 SKIP BO 9 6 FB COMP OVP 7 8 Pin Descriptions PIN I/O SYMBOL DESCRIPTION 1, 13 - NC Not Connected. Must be floating. 2 - GND Ground pin. All voltage levels refer to this pin. 3 I ISEN Current sense pin. The current through this pin is proportional to the inductor current. 4 I/O ICOMP Current error amplifier output pin. 5 I VIN Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider from the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the input current. The phase lag is required to compensate the phase lead generated by the EMI filter. 6 I/O BO This pin should be decoupled to GND with a minimum 0.1F ceramic capacitor. The BO pin is a voltage follower, which will follow the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor R . The decoupling capacitor IS provides ripple filtering. When the voltage at the BO pin (V ) drops below brownout voltage threshold, the controller BO enters shutdown mode and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling threshold. 7 I OVP Overvoltage protection pin. Connect this pin to a resistor divider from the output. The resistor divider sets the OVP set point. When the OVP pin voltage exceeds 104.5% of the reference voltage V , OVP is triggered and the gate drive is disabled. REF 8 I/O COMP Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will slowly ramp up the voltage of the COMP pin. 9 I FB Voltage feedback pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage. When the FB pin voltage exceeds 104% of V , OVP is triggered and gate drive is disabled. When the FB pin drops below REF 10% of V , the device is put into shutdown mode. There is an internal pull-down current source for open loop protection. REF 10 I/O SKIP This pin has dual functions. Connecting this pin to ground disables the light load skip function. An internal 20A current sources out of this pin. Connect a resistor from this pin to the ground to set the average power trip point. The converter exits the skip mode when either the VFB drops below 88% of V , or the ISEN current goes above 29 A. REF 11 - VREG Output of internal regulator. The voltage having a 2% tolerance over line, load and operating temperature. Bypass to GND with a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass. 12 I VCC Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1F ceramic capacitor. 14 O GATE Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and 1.5A source capability. FN8582 Rev 1.00 Page 2 of 20 February 13, 2015