NOT RECOMMENDED FOR NEW DESIGNS DATASHEET PLEASE SEE ISL6744A ISL6744 FN9147 Rev.8.00 Intermediate Bus PWM Controller September 22, 2005 The ISL6744 is a low cost, primary side, double-ended Features controller intended for applications using full and half-bridge Precision Duty Cycle and Deadtime Control topologies for unregulated DC/DC converters. It is a voltage- mode PWM controller designed for half-bridge and full- 100A Start-up Current bridge power supplies. It provides precise control of Adjustable Delayed Overcurrent Shutdown and Restart switching frequency, adjustable soft-start, precise deadtime Adjustable Oscillator Frequency Up to 2MHz control with deadtimes as low as 35ns, and overcurrent shutdown. 1A MOSFET Gate Drivers Low start-up and operating currents allow for easy biasing in Adjustable Soft-Start both AC/DC and DC/DC applications. This advanced Internal Over Temperature Protection BiCMOS design features low start-up and operating currents, adjustable switching frequency up to 1MHz, 1A 35ns Control to Output Propagation Delay FET drivers, and very low propagation delays for a fast Small Size and Minimal External Component Count response to overcurrent faults. Input Undervoltage Protection Ordering Information Pb-Free Plus Anneal Available (RoHS Compliant) TEMP. PKG. PART NUMBER RANGE (C) PACKAGE DWG. Applications ISL6744AU -40 to 105 8 Ld MSOP M8.118 Telecom and Datacom Isolated Power ISL6744AUZ -40 to 105 8 Ld MSOP M8.118 DC Transformers (Note) (Pb-free) Bus Converters ISL6744AB -40 to 105 8 Ld SOIC M8.15 ISL6744ABZ -40 to 105 8 Ld SOIC M8.15 Pinout (Note) (Pb-free) ISL6744 (SOIC, MSOP) TOP VIEW Add -T suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% SS 1 8 VDD matte tin plate termination finish, which are RoHS compliant and RTD 2 7 OUTB compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow CS 3 6 OUTA temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5 GND CT 4 FN9147 Rev.8.00 Page 1 of 18 September 22, 2005ISL6744 FN9147 Rev.8.00 Page 2 of 18 September 22, 2005 V DD FL Internal Architecture V BIAS V V BIAS DD 5.00 V OUTA Q T UVLO + Q OUTB - PWM TOGGLE V INTERNAL BIAS BG OT SHUTDOWN 130 - 150 C 70uA GND ON SS V BIAS + SS CLAMP - 15 uA R 2.0 V - + SS CHARGED 3.9 V TD I RTD + - 4.0 V S Q V BIAS R Q 160 uA OC LATCH ON - 2.8 V PEAK CLK S Q + R Q C Q T RESET - VALLEY DOMINANT Q SS LOW 0.27 V + 0.8 V + 50 S - RETRIGGERABLE ONE SHOT SS FAULT LATCH SET DOMINANT S Q S Q FL I DCH R Q R Q PWM LATCH ON V SET BIAS DOMINANT V UV - BIAS + 4.65V 4.80V BG OC DETECT CS + - 0.6 V SS COMPARATOR + C T - SS 0.8 I = 55 x I DCH RTD