ISL78302AARJCZ Renesas

DATASHEET ISL78302A FN7932 Rev 2.00 Dual LDO with Low Noise, Very High PSRR and Low IQ December 22, 2015 ISL78302A is a high-performance dual LDO capable of Features sourcing 300mA current from each output. It has a low Integrates Two 300mA High-performance LDOs standby current and very high PSRR and is stable with output capacitance of 1F to 10F with ESR of up to 200m. Excellent Transient Response to Large Current Steps The device integrates an individual Power-On Reset (POR) 1.8% Accuracy Over All Operating Conditions function for each output. The POR delay for VO2 can be Excellent Load Regulation: < 0.1% Voltage Change Across externally programmed by connecting a timing capacitor to the Full Range of Load Current CPOR pin. The POR delay for VO1 is internally fixed at Low Output Noise: Typically 30V at 100A (1.5V) RMS approximately 2ms. A reference bypass pin is also provided for connecting a noise-filtering capacitor for low noise and Very High PSRR: 90dB at 1kHz high-PSRR applications. Extremely Low Quiescent Current: 47A (Both LDOs Active) The quiescent current is typically only 47A with both LDOs Wide Input Voltage Capability: 2.3V to 6.5V enabled and active. Separate Enable pins control each Low Dropout Voltage: Typically 230mV at 300mA individual LDO output. When both Enable pins are low, the device is in shutdown, typically drawing less than 0.3A. Stable with 1F to 10F Ceramic Capacitors Separate Enable and POR Pins for Each LDO The ISL78302A is AEC-Q100 qualified. The ISL78302A is rated for the automotive temperature range (-40C to +105C). Soft-start and Staged Turn-on to Limit Input Current Surge During Enable Current Limit and Overheat Protection Tiny 10 Ld 3mmx3mm DFN Package -40C to +105C Operating Temperature Range Pb-free (RoHS Compliant) AEC-Q100 Qualified Applications Radio Receivers Camera Modules GPS/Navigation Infotainment Systems ISL78302A 10 1 VIN (2.3 TO 6.5V) VIN VO1 V OUT1 ON 9 2 EN1 VO2 V ENABLE1 OUT2 V OK ON OUT2 OFF 8 3 EN2 POR2 ENABLE2 RESET2 OFF 4 7 V TOO LOW (200ms DELAY, OUT2 CBYP POR1 C3 = 0.01F) V OK OUT1 5 6 GND CPOR RESET1 (2ms DELAY) C1 C2 C3 C4 C5 V TOO LOW OUT1 C1, C4, C5: 1F X5R CERAMIC CAPACITOR C2: 0.1F X7R CERAMIC CAPACITOR C3: 0.01F X7R CERAMIC CAPACITOR FIGURE 1. TYPICAL APPLICATION FN7932 Rev 2.00 Page 1 of 12 December 22, 2015ISL78302A Block Diagram VIN VO1 VO2 LDO VO1 ERROR AMPLIFIER ~1.0V VO2 VREF TRIM POR COMPARATOR IS1 QEN1 1V VOK1 VOK2 POR1 LDO-1 POR2 LDO-2 VO2 EN1 CONTROL POR2 LOGIC POR2 VOK2 EN2 DELAY CBYP VO1 BANDGAP AND TEMPERATURE UVLO SENSOR POR1 POR1 1.00V VOLTAGE VOK1 DELAY REFERENCE 0.94V GENERATOR 0.90V GND CPOR FN7932 Rev 2.00 Page 2 of 12 December 22, 2015 IS1 IS2 QEN1 QEN2 100k 100k