DATASHEET ISL78424, ISL78434, ISL78444 FN9357 Rev.0.00 100V Boot, 4A Peak, Half-Bridge Driver with Single PWM Input and Adaptive Sep 10, 2018 Dead Time Control The ISL78424, ISL78434, and ISL78444 are Automotive Features Grade (AEC-Q100 Grade 1) high voltage, high Patented gate-sensed adaptive dead time control frequency, half-bridge NMOS FET drivers for driving provides shoot-through protection and mimized dead the gates of up to 70V half-bridge topologies. time The family of half-bridge drivers feature 3A sourcing, Unique tri-level PWM input for integration with 4A sinking peak gate drive current. The ISL78424 and Renesas multiphase controllers (for example, ISL78444 feature a single tri-level PWM input for ISL78225 and ISL78226) controlling both gate drivers. The ISL78434 has dual 3A sourcing and 4A sinking output current independent inputs for controlling the high-side and On-chip 3 bootsrap FET switch low-side driver separately. The ISL78424 and ISL78434 have independent sourcing and sinking pins for each gate Programmable dead time delay with single resistor driver while ISL78444 has a single combined Tri-level PWM input (ISL78424, ISL78444) sourcing/sinking output for each gate driver. Independent HI/LI inputs (ISL78434) Strong gate drive strength and the Adaptive Dead Time Separate source/sink pins at driver outputs (ADT) feature allow this family of drivers to switch high (ISL78424, ISL78434) voltage, low r power FETs in half-bridge DS(ON) topologies at high operating frequencies while providing Bootstrap and VDD Undervoltage Lockout (UVLO) shoot-through protection and minimizing dead time Wide supply range: 8V to 18V switching losses. Bootstrap supply maximum voltage: 100V The ISL78424, ISL78434, and ISL78444 are offered in a 14 Maximum phase voltage: 86V Ld HTSSOP package that complies with 100V conductor spacing per IPC-2221B. The ISL78444 is pin compatible Minimum phase voltage: -10V with the ISL78420. All devices are specified across a Applications wide ambient temperature range of -40C to +140C. Automotive half-bridge and 3-phase motor driver Related Literature 12V to 24V and 12V to 48V bidirectional DC/DC For a full list of related documents, visit our website: (with ISL78226, ISL78224 controllers) ISL78424, ISL78434, ISL78444 product pages Multi-phase boost (with ISL78220 and ISL78225 controllers) V BUS 12V 48V R SINK PWM LO R SOURCE CBOOT VDD VOUT HB 1 14 VDD HB EN R ISL78444 SOURCE HO H LO H HO RDT 2 13 PWM1 VSS HS HO L LO L 3 12 EPAD PWM2 R ISL78226 SINK HS VSS PWM3 11 4 6-Phase ISL78424 PWM4 DC/DC Phase 1 PWM NC 5 10 Controller PWM5 From Phase 2 EN Controller PWM6 NC 6 9 Phase 3 AGND RDT Phase 4 7 8 Phase 5 Phase 6 Figure 1. Independent Source and Sink Outputs for Figure 2. NMOS Half-Bridge Driver for 12V-48V Bi-Directional Optimizing Gate Drive Current and Adaptive Dead Time DC/DC Controller Sensing FN9357 Rev.0.00 Page 1 of 34 Sep 10, 2018ISL78424, ISL78434, ISL78444 Contents 1. Overview . 3 1.1 Block Diagrams . 3 1.2 Ordering Information . 6 1.3 Pin Configurations . 6 1.4 Pin Descriptions . 7 2. Specifications . 8 2.1 Absolute Maximum Ratings 8 2.2 Thermal Information 8 2.3 Recommended Operating Conditions 8 2.4 Electrical Specifications . 9 2.5 Switching Specifications . 11 2.6 Timing Diagrams . 13 3. Typical Performance Curves 15 4. Product Description . 20 4.1 Single PWM or Independent HI/LI Inputs 20 4.2 ISL78424 and ISL78444 PWM Input 20 4.3 ISL78434 HI/LI Lockout Protection . 21 4.4 Separate Source and Sink Outputs . 21 4.5 Peak Gate Drive Currents 22 4.6 Shoot-Through Protection 23 4.7 Shoot-Through and Dead Time 23 4.8 Adaptive Dead Time Control (ADTC) 23 4.9 Adaptive Dead Time and Gate Resistors . 24 4.10 Falling Thresholds for ADTC 25 4.11 Adjustable Dead Time Delay (RDT Pin) . 25 4.12 Integrated Bootstrap Switch . 26 4.13 Bootstrap Capacitor . 26 4.14 EN Pin . 27 4.15 UVLO Protection - VDD and Boot 27 5. Applications Information . 28 5.1 Supply Voltage Operating Range 28 5.2 Bootstrap Capacitor Design . 28 5.3 Gate Drive Limiting Resistors . 28 5.4 Adaptive Dead Time Control 29 5.5 Adjustable Dead Time Control . 29 5.6 Power Dissipation Calculation . 29 6. PCB Layout Guidelines 31 7. Revision History 32 8. Package Outline Drawing 33 FN9357 Rev.0.00 Page 2 of 34 Sep 10, 2018